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corrections in appnote

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Ahmed Irfan 2014-11-03 16:18:53 +01:00
parent 6c6cdf736a
commit 3dd316bdc7
1 changed files with 2 additions and 1 deletions
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manual/APPNOTE_012_Verilog_to_BTOR.tex
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@ -150,7 +150,8 @@ endmodule
\begin{figure}[H]
\begin{lstlisting}[language=Verilog]
module test(input clk, input rst, output y);
module test(input clk, input rst, output y,
output safety1);
reg [2:0] state;
output safety1;
always @(posedge clk) begin