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inline all tests. Add switch to remove init values as PolarFire DFFs do not support init

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chunlin min 2024-07-08 17:03:03 -04:00
parent 0afb5e28fb
commit 3db69b7a10
15 changed files with 152 additions and 288 deletions
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25
tests/arch/microchip/uram_sr.ys
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@ -14,7 +14,30 @@
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog uram_sr.v
read_verilog <<EOT
module uram_sr(clk, wr, raddr, din, waddr, dout);
input clk;
input [11:0] din;
input wr;
input [5:0] waddr, raddr;
output [11:0] dout;
reg [5:0] raddr_reg;
reg [11:0] mem [0:63];
assign dout = mem[raddr_reg];
integer i;
initial begin
for (i = 0; i < 64; i = i + 1) begin
mem[i] = 12'hfff;
end
end
always@(posedge clk) begin
raddr_reg <= raddr;
if(wr)
mem[waddr]<= din;
end
endmodule
EOT
synth_microchip -top uram_sr -family polarfire -noiopad