mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-17 00:32:17 +00:00
Code Activity

inline all tests. Add switch to remove init values as PolarFire DFFs do not support init

Browse source
This commit is contained in:
chunlin min 2024-07-08 17:03:03 -04:00
parent 0afb5e28fb
commit 3db69b7a10
15 changed files with 152 additions and 288 deletions
Download patch file Download diff file Expand all files Collapse all files

22
tests/arch/microchip/ram_SDP.ys
View file

@ -14,7 +14,27 @@
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog ram_SDP.v
read_verilog <<EOT
module ram_SDP(data,waddr,we,clk,q);
parameter d_width = 32;
parameter addr_width = 8;
parameter mem_depth = 256;
input [d_width-1:0] data;
input [addr_width-1:0] waddr;
input we, clk;
output reg [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
always @(posedge clk) begin
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
end
end
endmodule
EOT
synth_microchip -top ram_SDP -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 1 t:CFG1