3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-17 08:42:16 +00:00

inline all tests. Add switch to remove init values as PolarFire DFFs do not support init

This commit is contained in:
chunlin min 2024-07-08 17:03:03 -04:00
parent 0afb5e28fb
commit 3db69b7a10
15 changed files with 152 additions and 288 deletions

View file

@ -14,10 +14,28 @@
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog dff_opt.v
# reset can be merged into D LUT
read_verilog <<EOT
module dff_opt(
input clk,
input [1:0] D_comb,
input [1:0] EN_comb,
input [1:0] RST_comb,
output bar
);
reg foo;
assign bar = foo;
always@(posedge clk) begin
if (&RST_comb) begin
foo <= 0;
end else begin
foo <= &D_comb;
end
end
endmodule
EOT
synth_microchip -top dff_opt -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CFG4
select -assert-count 1 t:CLKBUF