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advanced_bugpoint.rst: --dump-design
Also fix missing double backtick.
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@ -213,16 +213,31 @@ in the right direction:
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Try running the unminimized script and search the log for the names of the
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Try running the unminimized script and search the log for the names of the
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objects in your minimized design. In the case of cells you can also search for
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objects in your minimized design. In the case of cells you can also search for
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the type of the cell. Remember that calling `stat` will list all the types of
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the type of the cell. Remember that calling `stat` will list all the types of
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cells currently used in the design, and `select -list =*` will list the names of
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cells currently used in the design, and ``select -list =*`` will list the names
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of all the current objects. You can add these commands to your script, or use
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of of all the current objects. You can add these commands to your script, or
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an interactive terminal to run each command individually. Adding them to the
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use an interactive terminal to run each command individually. Adding them to
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script can be more repeatable, but if it takes a long time to run to the point
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the script can be more repeatable, but if it takes a long time to run to the
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you're interested in then an interactive shell session can give you more
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point you're interested in then an interactive shell session can give you more
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flexibility once you reach that point. You can also add a call to the `shell`
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flexibility once you reach that point. You can also add a call to the `shell`
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command at any point in a script to start an interactive session at a given
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command at any point in a script to start an interactive session at a given
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point; allowing you to script any preparation steps, then come back once it's
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point; allowing you to script any preparation steps, then come back once it's
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done.
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done.
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The ``--dump-design`` option
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Yosys provides the ``--dump-design`` option (or ``-P`` for short) for dumping
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the design at specific steps of the script based on the log header. If the last
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step before an error is ``7.2. Executing MEMORY_MAP pass (converting memories to
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logic and flip-flops)``, then calling Yosys with ``--dump-design 7.2:bad.il``
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will save the design *before* this command runs, in the file ``bad.il``.
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It is also possible to use this option multiple times, e.g. ``-P2:hierarchy.il
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-P7 -P7.2:bad.il``, to get multiple dumps in the same run. This can make it
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easier to follow the design through each step to find where certain cells or
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connections are coming from. ``--dump-design ALL`` is also allowed, writing out
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the design at each log header.
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A worked example
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A worked example
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~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~
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