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@ -406,7 +406,42 @@ input values to cells.
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\subsubsection{Handling shorted inputs}
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\begin{frame}{\subsubsecname}
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TBD
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\begin{itemize}
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\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
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{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
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\medskip
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\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
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number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
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\medskip
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\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
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\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
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\medskip
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\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
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\medskip
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\item Example use-cases:
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\begin{itemize}
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\item Detecting shared clock or control signals in memory interfaces.
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\item In some cases this can be used for for optimization.
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\end{itemize}
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\end{itemize}
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\end{frame}
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\begin{frame}[t]{\subsubsecname{} -- Example}
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\vbox to 0cm{
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\vskip4.5cm
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\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
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\vss
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}
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\vskip-0.6cm
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\begin{columns}
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\column[t]{6cm}
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\vskip-0.4cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
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\column[t]{4.2cm}
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\vskip-0.6cm
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
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\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
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\end{columns}
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\end{frame}
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\subsubsection{Notes on using techmap}
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