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Progress in presentation

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Clifford Wolf 2014-02-18 19:37:39 +01:00
parent a71d09421d
commit 3d9da919d8
6 changed files with 72 additions and 3 deletions
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5
manual/PRESENTATION_ExAdv/Makefile
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@ -1,5 +1,5 @@
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
@ -16,3 +16,6 @@ mymul.pdf: mymul_*
mulshift.pdf: mulshift_*
../../yosys mulshift_test.ys
addshift.pdf: addshift_*
../../yosys addshift_test.ys

20
manual/PRESENTATION_ExAdv/addshift_map.v Normal file
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module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
parameter _TECHMAP_CONNMAP_B_ = 0;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
assign Y = A << 1;
endmodule

5
manual/PRESENTATION_ExAdv/addshift_test.v Normal file
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module test (A, B, X, Y);
input [7:0] A, B;
output [7:0] X = A + B;
output [7:0] Y = A + A;
endmodule

6
manual/PRESENTATION_ExAdv/addshift_test.ys Normal file
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read_verilog addshift_test.v
hierarchy -check -top test
techmap -map addshift_map.v;;
show -prefix addshift -format pdf -notitle