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Improve src tagging (using names and attrs) of cells and wires in verific front-end

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-12-18 16:01:22 +01:00
parent 847fd36077
commit 3d671630e2
2 changed files with 160 additions and 99 deletions
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frontends/verific/verific.h
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@ -78,6 +78,7 @@ struct VerificImporter
RTLIL::SigBit net_map_at(Verific::Net *net);
RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj);
RTLIL::SigSpec operatorInput(Verific::Instance *inst);