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memory_map: propagate Mem src onto every generated cell

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This commit is contained in:
Emil J. Tywoniak 2026-06-03 00:56:53 +02:00
parent 7656347b44
commit 3d27e83d0f
2 changed files with 20 additions and 6 deletions
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14
passes/memory/memory_map.cc
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@ -42,6 +42,10 @@ struct MemoryMapWorker
std::map<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>, RTLIL::SigBit> decoder_cache;
// src of the Mem currently being lowered, so every cell created on its
// behalf inherits source-location tracking from the original $mem_v2.
std::string mem_src;
MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), sigmap(module), initvals(&sigmap, module) {}
std::string map_case(std::string value) const
@ -89,12 +93,12 @@ struct MemoryMapWorker
if (decoder_cache.count(key) == 0) {
if (GetSize(addr_sig) < 2) {
decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val);
decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val, false, mem_src);
} else {
int split_at = GetSize(addr_sig) / 2;
RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at));
RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at));
decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq);
decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq, false, mem_src);
}
}
@ -108,6 +112,8 @@ struct MemoryMapWorker
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
mem_src = mem.get_src_attribute();
SigSpec init_data = mem.get_init_data();
if (!mem.wr_ports.empty() && rom_only)
@ -238,6 +244,7 @@ struct MemoryMapWorker
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
c->setPort(ID::CLK, refclock);
}
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = mem.width;
RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", addr, "$d"), mem.width);
@ -292,6 +299,7 @@ struct MemoryMapWorker
for (size_t k = 0; k < rd_signals.size(); k++)
{
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = GetSize(port.data);
c->setPort(ID::Y, rd_signals[k]);
c->setPort(ID::S, rd_addr.extract(abits-j-1, 1));
@ -351,6 +359,7 @@ struct MemoryMapWorker
if (wr_bit != State::S1)
{
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wren", addr, "", j, "", wr_offset), ID($and));
c->set_src_attribute(mem_src);
c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
@ -364,6 +373,7 @@ struct MemoryMapWorker
}
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = wr_width;
c->setPort(ID::A, sig.extract(wr_offset, wr_width));
c->setPort(ID::B, port.data.extract(wr_offset + sub * mem.width, wr_width));