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memory_map: propagate Mem src onto every generated cell
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parent
7656347b44
commit
3d27e83d0f
2 changed files with 20 additions and 6 deletions
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@ -888,6 +888,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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if (!port.clk_enable)
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return nullptr;
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std::string mem_src = get_src_attribute();
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Cell *c;
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// There are two ways to handle rdff extraction when transparency is involved:
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@ -934,7 +936,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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port.addr[i] = sig_q[pos++];
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}
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c = module->addDff(stringf("$%s$rdreg[%d]", memid, idx), port.clk, sig_d, sig_q, port.clk_polarity);
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c = module->addDff(stringf("$%s$rdreg[%d]", memid, idx), port.clk, sig_d, sig_q, port.clk_polarity, mem_src);
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} else {
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c = nullptr;
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}
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@ -966,7 +968,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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raddr = port.sub_addr(sub);
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SigSpec addr_eq;
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if (raddr != waddr)
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addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid, idx, i, sub), raddr, waddr);
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addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid, idx, i, sub), raddr, waddr, false, mem_src);
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int pos = 0;
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int ewidth = width << min_wide_log2;
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int wsub = wide_write ? sub : 0;
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@ -979,10 +981,10 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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SigSpec other = port.transparency_mask[i] ? wport.data.extract(pos + wsub * width, epos-pos) : Const(State::Sx, epos-pos);
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SigSpec cond;
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if (raddr != waddr)
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cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq);
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cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq, false, mem_src);
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else
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cond = wport.en[pos + wsub * width];
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SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), cur, other, cond);
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SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), cur, other, cond, mem_src);
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sig_d.replace(pos + rsub * width, merged);
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pos = epos;
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}
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@ -992,6 +994,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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IdString name = stringf("$%s$rdreg[%d]", memid, idx);
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FfData ff(module, initvals, name);
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if (!mem_src.empty())
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ff.attributes[ID::src] = mem_src;
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ff.width = GetSize(port.data);
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ff.has_clk = true;
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ff.sig_clk = port.clk;
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