mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-07 06:33:24 +00:00
Code Activity

Merge pull request #513 from udif/pr_reg_wire_error

Browse source 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
This commit is contained in:
Clifford Wolf 2018-08-15 13:35:41 +02:00 • committed by GitHub
commit 3d27c1cc80
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
7 changed files with 132 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/verilog/verilog_lexer.l
View file

@ -192,7 +192,7 @@ YOSYS_NAMESPACE_END
"const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
"checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
"logic" { SV_KEYWORD(TOK_REG); }
"logic" { SV_KEYWORD(TOK_LOGIC); }
"bit" { SV_KEYWORD(TOK_REG); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }