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Merge pull request #513 from udif/pr_reg_wire_error

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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
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Clifford Wolf 2018-08-15 13:35:41 +02:00 • committed by GitHub
commit 3d27c1cc80
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7 changed files with 132 additions and 4 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -192,7 +192,7 @@ YOSYS_NAMESPACE_END
"const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
"checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
"logic" { SV_KEYWORD(TOK_REG); }
"logic" { SV_KEYWORD(TOK_LOGIC); }
"bit" { SV_KEYWORD(TOK_REG); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }

7
frontends/verilog/verilog_parser.y
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@ -105,7 +105,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@ -397,6 +397,9 @@ wire_type_token:
TOK_REG {
astbuf3->is_reg = true;
} |
TOK_LOGIC {
astbuf3->is_logic = true;
} |
TOK_INTEGER {
astbuf3->is_reg = true;
astbuf3->range_left = 31;
@ -548,6 +551,7 @@ task_func_decl:
AstNode *outreg = new AstNode(AST_WIRE);
outreg->str = *$6;
outreg->is_signed = $4;
outreg->is_reg = true;
if ($5 != NULL) {
outreg->children.push_back($5);
outreg->is_signed = $4 || $5->is_signed;
@ -1027,6 +1031,7 @@ wire_name:
node->port_id = current_function_or_task_port_id++;
}
ast_stack.back()->children.push_back(node);
delete $1;
};