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Merge pull request #513 from udif/pr_reg_wire_error

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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
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Clifford Wolf 2018-08-15 13:35:41 +02:00 • committed by GitHub
commit 3d27c1cc80
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7 changed files with 132 additions and 4 deletions
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frontends/ast/ast.h
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@ -168,7 +168,7 @@ namespace AST
// node content - most of it is unused in most node types
std::string str;
std::vector<RTLIL::State> bits;
bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped;
bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked;
int port_id, range_left, range_right;
uint32_t integer;
double realvalue;