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Merge pull request #513 from udif/pr_reg_wire_error

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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
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Clifford Wolf 2018-08-15 13:35:41 +02:00 • committed by GitHub
commit 3d27c1cc80
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7 changed files with 132 additions and 4 deletions
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8
frontends/ast/ast.cc
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@ -191,8 +191,10 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
is_input = false;
is_output = false;
is_reg = false;
is_logic = false;
is_signed = false;
is_string = false;
was_checked = false;
range_valid = false;
range_swapped = false;
port_id = 0;
@ -285,7 +287,9 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
fprintf(f, " input");
if (is_output)
fprintf(f, " output");
if (is_reg)
if (is_logic)
fprintf(f, " logic");
if (is_reg) // this is an AST dump, not Verilog - if we see "logic reg" that's fine.
fprintf(f, " reg");
if (is_signed)
fprintf(f, " signed");
@ -652,6 +656,8 @@ bool AstNode::operator==(const AstNode &other) const
return false;
if (is_output != other.is_output)
return false;
if (is_logic != other.is_logic)
return false;
if (is_reg != other.is_reg)
return false;
if (is_signed != other.is_signed)