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Read init from outputs

This commit is contained in:
Eddie Hung 2019-06-15 22:41:42 -07:00
parent d969a9060e
commit 3d1185b835

View file

@ -927,6 +927,10 @@ void AigerReader::post_process()
}
}
log_debug(" -> %s\n", log_id(wire));
int init;
mf >> init;
if (init < 2)
wire->attributes["\\init"] = init;
}
else if (type == "box") {
RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));