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Read init from outputs
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@ -927,6 +927,10 @@ void AigerReader::post_process()
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}
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}
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log_debug(" -> %s\n", log_id(wire));
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int init;
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mf >> init;
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if (init < 2)
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wire->attributes["\\init"] = init;
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}
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
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