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reorder verilog backend port wires

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This commit is contained in:
Hongce Zhang 2025-08-07 11:37:23 +08:00
parent 15b4716d18
commit 3cbbb9456d
1 changed files with 13 additions and 1 deletions
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14
backends/verilog/verilog_backend.cc
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@ -2358,12 +2358,16 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
int cnt = 0;
std::vector<Wire *> port_ordered;
for (auto port : module->ports) {
Wire *wire = module->wire(port);
if (wire) {
if (port != module->ports[0])
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
port_ordered.push_back(wire);
if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
continue;
}
@ -2374,9 +2378,17 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}
for (auto w : module->wires())
// first dump input / output according to port_ordered;
for (auto w : port_ordered)
dump_wire(f, indent + " ", w);
for (auto w : module->wires()) {
// avoid duplication
if (std::find(port_ordered.begin(), port_ordered.end(), w) != port_ordered.end())
continue;
dump_wire(f, indent + " ", w);
}
for (auto &mem : Mem::get_all_memories(module))
dump_memory(f, indent + " ", mem);