From 3cbbb9456d57943495a67bcb79a3ab1b8c9e18ea Mon Sep 17 00:00:00 2001 From: Hongce Zhang Date: Thu, 7 Aug 2025 11:37:23 +0800 Subject: [PATCH] reorder verilog backend port wires --- backends/verilog/verilog_backend.cc | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 070df1543..b49927513 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2358,12 +2358,16 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); int cnt = 0; + + std::vector port_ordered; + for (auto port : module->ports) { Wire *wire = module->wire(port); if (wire) { if (port != module->ports[0]) f << stringf(", "); f << stringf("%s", id(wire->name).c_str()); + port_ordered.push_back(wire); if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; continue; } @@ -2374,8 +2378,16 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << indent + " " << "reg " << id(initial_id) << " = 0;\n"; } - for (auto w : module->wires()) + // first dump input / output according to port_ordered; + for (auto w : port_ordered) dump_wire(f, indent + " ", w); + + for (auto w : module->wires()) { + // avoid duplication + if (std::find(port_ordered.begin(), port_ordered.end(), w) != port_ordered.end()) + continue; + dump_wire(f, indent + " ", w); + } for (auto &mem : Mem::get_all_memories(module)) dump_memory(f, indent + " ", mem);