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move attributes to wires

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This commit is contained in:
Marcin Kościelnicki 2019-08-13 19:36:59 +00:00
parent 49765ec19e
commit 3c75a72feb
8 changed files with 555 additions and 320 deletions
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6
techlibs/xilinx/xc7_brams_bb.v
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@ -1,6 +1,7 @@
(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
module RAMB18E1 (
(* clkbuf_sink *)
input CLKARDCLK,
(* clkbuf_sink *)
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
@ -123,9 +124,10 @@ module RAMB18E1 (
parameter SIM_DEVICE = "VIRTEX6";
endmodule
(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
module RAMB36E1 (
(* clkbuf_sink *)
input CLKARDCLK,
(* clkbuf_sink *)
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,