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move attributes to wires

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This commit is contained in:
Marcin Kościelnicki 2019-08-13 19:36:59 +00:00
parent 49765ec19e
commit 3c75a72feb
8 changed files with 555 additions and 320 deletions
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6
techlibs/xilinx/xc6s_brams_bb.v
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@ -1,6 +1,7 @@
(* clkbuf_sink = "CLKAWRCLK,CLKBRDCLK" *)
module RAMB8BWER (
(* clkbuf_sink *)
input CLKAWRCLK,
(* clkbuf_sink *)
input CLKBRDCLK,
input ENAWREN,
input ENBRDEN,
@ -87,9 +88,10 @@ module RAMB8BWER (
parameter SIM_COLLISION_CHECK = "ALL";
endmodule
(* clkbuf_sink = "CLKA,CLKB" *)
module RAMB16BWER (
(* clkbuf_sink *)
input CLKA,
(* clkbuf_sink *)
input CLKB,
input ENA,
input ENB,