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move attributes to wires

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This commit is contained in:
Marcin Kościelnicki 2019-08-13 19:36:59 +00:00
parent 49765ec19e
commit 3c75a72feb
8 changed files with 555 additions and 320 deletions
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24
passes/techmap/clkbufmap.cc
View file

@ -112,27 +112,13 @@ struct ClkbufmapPass : public Pass {
for (auto module : modules_sorted)
{
if (module->get_blackbox_attribute()) {
auto it = module->attributes.find("\\clkbuf_driver");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split_tokens(value, ",")) {
auto wire = module->wire(RTLIL::escape_id(name));
if (!wire)
log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
for (auto wire : module->wires()) {
if (wire->get_bool_attribute("\\clkbuf_driver"))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
}
}
it = module->attributes.find("\\clkbuf_sink");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split_tokens(value, ",")) {
auto wire = module->wire(RTLIL::escape_id(name));
if (!wire)
log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
if (wire->get_bool_attribute("\\clkbuf_sink"))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
}
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
}
continue;
}

13
passes/techmap/iopadmap.cc
View file

@ -173,15 +173,10 @@ struct IopadmapPass : public Pass {
ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
for (auto module : design->modules())
{
auto it = module->attributes.find("\\iopad_external_pin");
if (it != module->attributes.end()) {
auto value = it->second.decode_string();
for (auto name : split_tokens(value, ",")) {
ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
}
}
}
if (module->get_blackbox_attribute())
for (auto wire : module->wires())
if (wire->get_bool_attribute("\\iopad_external_pin"))
ignore.insert(make_pair(module->name, wire->name));
for (auto module : design->selected_modules())
{