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fix test setup for synth_quicklogic memory tests

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This commit is contained in:
N. Engelhardt 2023-12-01 10:47:39 +01:00 • committed by Martin Povišer
parent 509d176523
commit 3c5b0ab164
5 changed files with 21 additions and 36 deletions
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2
tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
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@ -8,7 +8,7 @@ parameter DATA_WIDTH_A = DATA_WIDTH;
parameter DATA_WIDTH_B = DATA_WIDTH;
parameter VECTORLEN = 16;
parameter SHIFT_VAL = 0;
localparam MAX_WIDTH = 36;
localparam MAX_WIDTH = DATA_WIDTH;
reg rce_a_testvector [VECTORLEN-1:0];
reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];