From 3c54d8aef791fbe000630ceb0e8af1c1f9f964ae Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 7 Jul 2025 10:38:32 +1200
Subject: [PATCH] tests/functional: Auto parallelize

Use the unique cell name (cell type + parameters) for the vcd filename to avoid collisions when converting to fst.
---
 tests/functional/conftest.py        |  2 +-
 tests/functional/rtlil_cells.py     |  5 +++--
 tests/functional/run-test.sh        |  2 +-
 tests/functional/test_functional.py | 12 ++++++------
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py
index a9fbb3c59..fb00d4f22 100644
--- a/tests/functional/conftest.py
+++ b/tests/functional/conftest.py
@@ -31,4 +31,4 @@ def pytest_generate_tests(metafunc):
         seed1 = metafunc.config.getoption("seed")
         rnd = lambda seed2: random.Random('{}-{}'.format(seed1, seed2))
         names, cases = generate_test_cases(per_cell, rnd)
-        metafunc.parametrize("cell,parameters", cases, ids=names)
+        metafunc.parametrize("name,cell,parameters", cases, ids=names)
diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py
index 964d81ddf..ab7cd4e0c 100644
--- a/tests/functional/rtlil_cells.py
+++ b/tests/functional/rtlil_cells.py
@@ -374,8 +374,9 @@ def generate_test_cases(per_cell, rnd):
         for (name, parameters) in cell.generate_tests(rnd):
             if not name in seen_names:
                 seen_names.add(name)
-                tests.append((cell, parameters))
-                names.append(f'{cell.name}-{name}' if name != '' else cell.name)
+                full_name = f'{cell.name}-{name}' if name != '' else cell.name
+                tests.append((full_name, cell, parameters))
+                names.append(full_name)
                 if per_cell is not None and len(seen_names) >= per_cell:
                     break
     return (names, tests)
\ No newline at end of file
diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh
index b9a0595f6..6786e93f1 100755
--- a/tests/functional/run-test.sh
+++ b/tests/functional/run-test.sh
@@ -1,2 +1,2 @@
 #!/usr/bin/env bash
-pytest -v "$@"
+pytest -v -n auto "$@"
diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py
index 86eabef1e..0553d6ecc 100644
--- a/tests/functional/test_functional.py
+++ b/tests/functional/test_functional.py
@@ -40,12 +40,12 @@ def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
             capture_output=True, check=False)
         raise
 
-def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
+def test_cxx(name, cell, parameters, tmp_path, num_steps, rnd):
     rtlil_file = tmp_path / 'rtlil.il'
     vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc'
     cc_file = tmp_path / 'my_module_functional_cxx.cc'
     vcdharness_exe_file = tmp_path / 'a.out'
-    vcd_functional_file = tmp_path / 'functional.vcd'
+    vcd_functional_file = tmp_path / f'{name}.vcd'
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
     cell.write_rtlil_file(rtlil_file, parameters)
@@ -56,12 +56,12 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
     yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
 
 @pytest.mark.smt
-def test_smt(cell, parameters, tmp_path, num_steps, rnd):
+def test_smt(name, cell, parameters, tmp_path, num_steps, rnd):
     import smt_vcd
 
     rtlil_file = tmp_path / 'rtlil.il'
     smt_file = tmp_path / 'smtlib.smt'
-    vcd_functional_file = tmp_path / 'functional.vcd'
+    vcd_functional_file = tmp_path / f'{name}.vcd'
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
     if hasattr(cell, 'smt_max_steps'):
@@ -75,12 +75,12 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
 
 @pytest.mark.rkt
 @pytest.mark.parametrize("use_assoc_list_helpers", [True, False])
-def test_rkt(cell, parameters, tmp_path, num_steps, rnd, use_assoc_list_helpers):
+def test_rkt(name, cell, parameters, tmp_path, num_steps, rnd, use_assoc_list_helpers):
     import rkt_vcd
 
     rtlil_file = tmp_path / 'rtlil.il'
     rkt_file = tmp_path / 'smtlib.rkt'
-    vcd_functional_file = tmp_path / 'functional.vcd'
+    vcd_functional_file = tmp_path / f'{name}.vcd'
     vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
 
     cell.write_rtlil_file(rtlil_file, parameters)