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Merge pull request #1338 from YosysHQ/eddie/deferred_top

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hierarchy -auto-top to work with (* top *) modules from read/read_verilog -defer
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Eddie Hung 2019-09-04 10:55:41 -07:00 • committed by GitHub
commit 3c462e5eeb
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3 changed files with 58 additions and 0 deletions
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7
frontends/ast/ast.cc
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@ -1099,6 +1099,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ignoreThisSignalsInInitial = RTLIL::SigSpec();
}
else {
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
continue;
current_module->attributes[attr.first] = attr.second->asAttrConst();
}
}
if (ast->type == AST_INTERFACE)
current_module->set_bool_attribute("\\is_interface");

24
passes/hierarchy/hierarchy.cc
View file

@ -808,6 +808,30 @@ struct HierarchyPass : public Pass {
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
IdString top_name = top_mod->name.substr(strlen("$abstract"));
dict<RTLIL::IdString, RTLIL::Const> top_parameters;
for (auto &para : parameters) {
SigSpec sig_value;
if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
log_cmd_error("Can't decode value '%s'!\n", para.second.c_str());
top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
}
top_mod = design->module(top_mod->derive(design, top_parameters));
if (top_mod != nullptr && top_mod->name != top_name) {
Module *m = top_mod->clone();
m->name = top_name;
Module *old_mod = design->module(top_name);
if (old_mod)
design->remove(old_mod);
design->add(m);
top_mod = m;
}
}
if (top_mod == nullptr && auto_top_mode) {
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;

27
tests/various/hierarchy_defer.ys Normal file
View file

@ -0,0 +1,27 @@
read -noverific
read -vlog2k <<EOT
module first;
endmodule
(* top *)
module top(input i, output o);
sub s0(i, o);
endmodule
(* constant_expression=1+1?2*2:3/3 *)
module sub(input i, output o);
assign o = ~i;
endmodule
EOT
design -save read
hierarchy -auto-top
select -assert-any top
select -assert-any sub
select -assert-none foo
design -load read
hierarchy
select -assert-any top
select -assert-any sub
select -assert-none foo