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genrtlil: intern action src as verbatim Twine

Browse source 
add(std::string) tags bare strings as public names, so a single-source
concat (which returns the lone ref unchanged) decoded with a spurious
'\' prefix, splitting one source file into two in linecoverage output.
add(Twine{}) stores the location string verbatim like set_src_attr.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
Emil J. Tywoniak 2026-06-24 17:39:13 +02:00
parent 58f95dbab8
commit 3c0056a4c1
1 changed files with 6 additions and 6 deletions
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12
frontends/ast/genrtlil.cc
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@ -624,7 +624,7 @@ struct AST_INTERNAL::ProcessGenerator
if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
remove_unwanted_lvalue_bits(lhs, rhs);
actions.push_back({lhs, rhs, ast ? current_module->design->twines.add(std::string{ast->loc_string()}) : Twine::Null});
actions.push_back({lhs, rhs, ast ? current_module->design->twines.add(Twine{ast->loc_string()}) : Twine::Null});
offset += lhs.size();
}
}
@ -680,7 +680,7 @@ struct AST_INTERNAL::ProcessGenerator
current_case_assigned_bits.insert(bit);
remove_unwanted_lvalue_bits(lvalue, rvalue);
current_case->actions.push_back({lvalue, rvalue, current_module->design->twines.add(std::string{ast->loc_string()})});
current_case->actions.push_back({lvalue, rvalue, current_module->design->twines.add(Twine{ast->loc_string()})});
}
break;
@ -830,8 +830,8 @@ struct AST_INTERNAL::ProcessGenerator
Wire *en = current_module->addWire(current_module->design->twines.add(std::string{sstr.str() + "_EN"}), 1);
set_src_attr(en, ast);
proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})});
current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})});
proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(Twine{ast->loc_string()})});
current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(Twine{ast->loc_string()})});
RTLIL::SigSpec triggers;
RTLIL::Const::Builder polarity_builder;
@ -928,8 +928,8 @@ struct AST_INTERNAL::ProcessGenerator
Wire *en = current_module->addWire(current_module->design->twines.add(std::string{cellname.str() + "_EN"}), 1);
set_src_attr(en, ast);
proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})});
current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})});
proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(Twine{ast->loc_string()})});
current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(Twine{ast->loc_string()})});
RTLIL::SigSpec triggers;
RTLIL::Const::Builder polarity_builder;