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Merge pull request #2006 from jersey99/signed-in-rtlil-wire

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Preserve 'signed'-ness of a verilog wire through RTLIL
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whitequark 2020-06-04 11:23:06 +00:00 • committed by GitHub
commit 3bffd09d64
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7 changed files with 19 additions and 2 deletions
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2
kernel/rtlil.cc
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@ -1862,6 +1862,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
wire->port_input = other->port_input;
wire->port_output = other->port_output;
wire->upto = other->upto;
wire->is_signed = other->is_signed;
wire->attributes = other->attributes;
return wire;
}
@ -2447,6 +2448,7 @@ RTLIL::Wire::Wire()
port_input = false;
port_output = false;
upto = false;
is_signed = false;
#ifdef WITH_PYTHON
RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));

2
kernel/rtlil.h
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@ -1368,7 +1368,7 @@ public:
RTLIL::Module *module;
RTLIL::IdString name;
int width, start_offset, port_id;
bool port_input, port_output, upto;
bool port_input, port_output, upto, is_signed;
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);