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Merge pull request #2006 from jersey99/signed-in-rtlil-wire

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Preserve 'signed'-ness of a verilog wire through RTLIL
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whitequark 2020-06-04 11:23:06 +00:00 • committed by GitHub
commit 3bffd09d64
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7 changed files with 19 additions and 2 deletions
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frontends/ilang/ilang_parser.y
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@ -192,6 +192,9 @@ wire_options:
wire_options TOK_UPTO {
current_wire->upto = true;
} |
wire_options TOK_SIGNED {
current_wire->is_signed = true;
} |
wire_options TOK_OFFSET TOK_INT {
current_wire->start_offset = $3;
} |