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Merge pull request #2006 from jersey99/signed-in-rtlil-wire

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Preserve 'signed'-ness of a verilog wire through RTLIL
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whitequark 2020-06-04 11:23:06 +00:00 • committed by GitHub
commit 3bffd09d64
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7 changed files with 19 additions and 2 deletions
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frontends/ast/genrtlil.cc
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@ -1065,6 +1065,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
wire->is_signed = is_signed;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)