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Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects

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This commit is contained in:
Clifford Wolf 2014-10-16 00:54:14 +02:00
parent 6b05a9e807
commit 3be5fa053f
1 changed files with 8 additions and 1 deletions
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9
kernel/rtlil.cc
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@ -2980,7 +2980,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
if (index_tokens.size() == 1) { if (index_tokens.size() == 1) {
cover("kernel.rtlil.sigspec.parse.bit_sel"); cover("kernel.rtlil.sigspec.parse.bit_sel");
sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str()))); int a = atoi(index_tokens.at(0).c_str());
if (a < 0 || a >= wire->width)
return false;
sig.append(RTLIL::SigSpec(wire, a));
} else { } else {
cover("kernel.rtlil.sigspec.parse.part_sel"); cover("kernel.rtlil.sigspec.parse.part_sel");
int a = atoi(index_tokens.at(0).c_str()); int a = atoi(index_tokens.at(0).c_str());
@ -2989,6 +2992,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
int tmp = a; int tmp = a;
a = b, b = tmp; a = b, b = tmp;
} }
if (a < 0 || a >= wire->width)
return false;
if (b < 0 || b >= wire->width)
return false;
sig.append(RTLIL::SigSpec(wire, a, b-a+1)); sig.append(RTLIL::SigSpec(wire, a, b-a+1));
} }
} else } else