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Fixed bug in $mem cell verilog code generation.

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This commit is contained in:
luke whittlesey 2015-05-11 14:05:18 -04:00
parent e47218e9ea
commit 3bb5f064b8
1 changed files with 12 additions and 11 deletions
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3
backends/verilog/verilog_backend.cc
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@ -903,7 +903,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool();
// group the wen bits
last_bit = sig_wr_en.extract(0);
lof_wen.append_bit(last_bit);
lof_wen = RTLIL::SigSpec(last_bit);
wen_to_width.clear();
wen_to_width[last_bit] = 0;
for (int j=0; j<width; j++)
{