mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Remove params from FD*_1 variants

Browse source
This commit is contained in:
Eddie Hung 2019-07-10 17:17:54 -07:00
parent 0372c900e8
commit 3bb48facb2
1 changed files with 3 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

15
techlibs/xilinx/abc_ff.v
View file

@ -98,10 +98,7 @@ endmodule
(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *) (* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ ); module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule endmodule
(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *) (* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
@ -116,10 +113,7 @@ endmodule
(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *) (* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ ); module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; assign Q = (CE && !CLR) ? D : \$pastQ ;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule endmodule
(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *) (* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
@ -134,10 +128,7 @@ endmodule
(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *) (* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ ); module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; assign Q = (CE && !PRE) ? D : \$pastQ ;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule endmodule
`endif `endif