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Addressed code review comments

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This commit is contained in:
Miodrag Milanovic 2023-08-25 11:10:20 +02:00
parent 541c1ab567
commit 3b9ebfa672
11 changed files with 21 additions and 104 deletions
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2
tests/arch/machxo2/add_sub.ys
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@ -1,7 +1,7 @@
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:LUT4