mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
		
							parent
							
								
									a440f82586
								
							
						
					
					
						commit
						3b796c033c
					
				
					 2 changed files with 9 additions and 1 deletions
				
			
		|  | @ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) | |||
| 		remove(width, width_ - width); | ||||
| 
 | ||||
| 	if (width_ < width) { | ||||
| 		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; | ||||
| 		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; | ||||
| 		if (!is_signed) | ||||
| 			padding = RTLIL::State::S0; | ||||
| 		while (width_ < width) | ||||
|  |  | |||
|  | @ -546,6 +546,14 @@ struct RTLIL::Const | |||
| 		return ret; | ||||
| 	} | ||||
| 
 | ||||
| 	void extu(int width) { | ||||
| 		bits.resize(width, RTLIL::State::S0); | ||||
| 	} | ||||
| 
 | ||||
| 	void exts(int width) { | ||||
| 		bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back()); | ||||
| 	} | ||||
| 
 | ||||
| 	inline unsigned int hash() const { | ||||
| 		unsigned int h = mkhash_init; | ||||
| 		for (auto b : bits) | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue