mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

xilinx: add delays to INV

Browse source
This commit is contained in:
Eddie Hung 2020-02-18 11:03:38 -08:00
parent 6bb3d9f9c0
commit 3b74e0fa45
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
techlibs/xilinx/cells_sim.v
View file

@ -160,6 +160,9 @@ module INV(
input I
);
assign O = !I;
specify
(I => O) = 127;
endspecify
endmodule
(* abc9_lut=1 *)