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xilinx: add delays to INV

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This commit is contained in:
Eddie Hung 2020-02-18 11:03:38 -08:00
parent 6bb3d9f9c0
commit 3b74e0fa45
1 changed files with 3 additions and 0 deletions
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3
techlibs/xilinx/cells_sim.v
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@ -160,6 +160,9 @@ module INV(
input I input I
); );
assign O = !I; assign O = !I;
specify
(I => O) = 127;
endspecify
endmodule endmodule
(* abc9_lut=1 *) (* abc9_lut=1 *)