mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-04-19 18:33:36 +00:00
Code Activity

fix $specrule port naming

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-04-13 16:48:27 +02:00
parent 413169663d
commit 3b64de3762
5 changed files with 5 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/common/simlib.v
View file

@ -1976,7 +1976,7 @@ endmodule
// --------------------------------------------------------
//* group spec
module \$specrule (EN_SRC, EN_DST, SRC, DST);
module \$specrule (SRC_EN, DST_EN, SRC, DST);
parameter TYPE = "";
parameter T_LIMIT = 0;
@ -1991,7 +1991,7 @@ parameter SRC_POL = 0;
parameter DST_PEN = 0;
parameter DST_POL = 0;
input EN_SRC, EN_DST;
input SRC_EN, DST_EN;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;