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now ignore init attributes on non-register wires in sat command

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This commit is contained in:
Clifford Wolf 2014-07-05 11:17:40 +02:00
parent ee8ad72fd9
commit 3b52121d32
3 changed files with 43 additions and 4 deletions
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4
tests/sat/initval.ys Normal file
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@ -0,0 +1,4 @@
read_verilog -sv initval.v
proc;;
sat -seq 10 -prove-asserts