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now ignore init attributes on non-register wires in sat command

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This commit is contained in:
Clifford Wolf 2014-07-05 11:17:40 +02:00
parent ee8ad72fd9
commit 3b52121d32
3 changed files with 43 additions and 4 deletions
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15
tests/sat/initval.v Normal file
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@ -0,0 +1,15 @@
module test(input clk, input [3:0] bar, output [3:0] foo);
reg [3:0] foo = 0;
reg [3:0] last_bar = 0;
always @*
foo[1:0] <= bar[1:0];
always @(posedge clk)
foo[3:2] <= bar[3:2];
always @(posedge clk)
last_bar <= bar;
assert property (foo == {last_bar[3:2], bar[1:0]});
endmodule