3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00

now ignore init attributes on non-register wires in sat command

This commit is contained in:
Clifford Wolf 2014-07-05 11:17:40 +02:00
parent ee8ad72fd9
commit 3b52121d32
3 changed files with 43 additions and 4 deletions

View file

@ -103,10 +103,30 @@ struct SatHelper
RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
log_assert(lhs.width == rhs.width);
log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
big_lhs.append(lhs);
big_rhs.append(rhs);
RTLIL::SigSpec removed_bits;
for (int i = 0; i < lhs.width; i++) {
RTLIL::SigSpec bit = lhs.extract(i, 1);
if (!satgen.initial_state.check_all(bit)) {
removed_bits.append(bit);
lhs.remove(i, 1);
rhs.remove(i, 1);
i--;
}
}
lhs.optimize();
rhs.optimize();
removed_bits.optimize();
if (removed_bits.width)
log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
if (lhs.width) {
log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
big_lhs.remove2(lhs, &big_rhs);
big_lhs.append(lhs);
big_rhs.append(rhs);
}
}
for (auto &s : sets_init)