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Merge pull request #1111 from acw1251/help_summary_fixes

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Fixed the help summary line for a few commands
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Eddie Hung 2019-06-19 15:30:50 -07:00 committed by GitHub
parent 96ade54993 ce29ede801
commit 3b1e5264d8
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 6 additions and 6 deletions
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2
passes/cmds/blackbox.cc
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@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct BlackboxPass : public Pass { struct BlackboxPass : public Pass {
BlackboxPass() : Pass("blackbox", "change type of cells in the design") { } BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

6
passes/sat/assertpmux.cc
View file

@ -180,7 +180,7 @@ struct AssertpmuxWorker
}; };
struct AssertpmuxPass : public Pass { struct AssertpmuxPass : public Pass {
AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { } AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@ -195,8 +195,8 @@ struct AssertpmuxPass : public Pass {
log("\n"); log("\n");
log(" -always\n"); log(" -always\n");
log(" usually the $pmux condition is only checked when the $pmux output\n"); log(" usually the $pmux condition is only checked when the $pmux output\n");
log(" is used be the mux tree it drives. this option will deactivate this\n"); log(" is used by the mux tree it drives. this option will deactivate this\n");
log(" additional constrained and check the $pmux condition always.\n"); log(" additional constraint and check the $pmux condition always.\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE

2
passes/sat/cutpoint.cc
View file

@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct CutpointPass : public Pass { struct CutpointPass : public Pass {
CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { } CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

2
techlibs/ice40/ice40_unlut.cc
View file

@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
} }
struct Ice40UnlutPass : public Pass { struct Ice40UnlutPass : public Pass {
Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { } Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|