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opt_clean: Remove init attribute bits together with removed DFFs.
Fixes #2546.
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2 changed files with 24 additions and 11 deletions
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@ -1,13 +1,22 @@
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logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
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logger -expect-no-warnings
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read_verilog <<EOT
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module top;
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(* init=1'b0 *) wire w = 1'b0;
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(* init=1'bx *) wire x = 1'b0;
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(* init=1'b1 *) wire y = 1'b0;
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(* init=1'b0 *) wire z = 1'bx;
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read_verilog << EOT
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module top(...);
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input [1:0] D;
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input C;
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output O;
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reg [1:0] Q;
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initial Q = 0;
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always @(posedge C)
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Q <= D;
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assign O = Q[1];
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endmodule
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EOT
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clean
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select -assert-count 1 a:init
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select -assert-count 1 w:y a:init %i
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synth
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check -assert -initdrv
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select -assert-count 1 a:init=2'b0x
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