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opt_clean: Remove init attribute bits together with removed DFFs.

Fixes #2546.
This commit is contained in:
Marcelina Kościelnicka 2021-03-09 21:32:16 +01:00
parent f965b3fa54
commit 3af871f969
2 changed files with 24 additions and 11 deletions

View file

@ -1,13 +1,22 @@
logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
logger -expect-no-warnings
read_verilog <<EOT
module top;
(* init=1'b0 *) wire w = 1'b0;
(* init=1'bx *) wire x = 1'b0;
(* init=1'b1 *) wire y = 1'b0;
(* init=1'b0 *) wire z = 1'bx;
read_verilog << EOT
module top(...);
input [1:0] D;
input C;
output O;
reg [1:0] Q;
initial Q = 0;
always @(posedge C)
Q <= D;
assign O = Q[1];
endmodule
EOT
clean
select -assert-count 1 a:init
select -assert-count 1 w:y a:init %i
synth
check -assert -initdrv
select -assert-count 1 a:init=2'b0x