mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-07 11:41:23 +00:00
Code Activity

added tests for new verilog features

Browse source
This commit is contained in:
Clifford Wolf 2014-06-07 12:18:00 +02:00
parent 744e518467
commit 3af7c69d1e
2 changed files with 38 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

30
tests/simple/repwhile.v
View file

@ -1,4 +1,5 @@
module test001(output [63:0] y);
module test001(input [5:0] a, output [7:0] y, output [31:0] x);
function [7:0] mylog2;
input [31:0] value;
begin
@ -10,11 +11,26 @@ module test001(output [63:0] y);
end
endfunction
genvar i;
generate
for (i = 0; i < 64; i = i+1) begin
localparam tmp = mylog2(i);
assign y[i] = tmp;
function [31:0] myexp2;
input [7:0] value;
begin
myexp2 = 1;
repeat (value)
myexp2 = myexp2 << 1;
end
endgenerate
endfunction
reg [7:0] y_table [63:0];
reg [31:0] x_table [63:0];
integer i;
initial begin
for (i = 0; i < 64; i = i+1) begin
y_table[i] <= mylog2(i);
x_table[i] <= myexp2(i);
end
end
assign y = y_table[a];
assign x = x_table[a];
endmodule