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added tests for new verilog features

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This commit is contained in:
Clifford Wolf 2014-06-07 12:18:00 +02:00
parent 744e518467
commit 3af7c69d1e
2 changed files with 38 additions and 7 deletions
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15
tests/simple/arraycells.v Normal file
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module test001(a, b, c, y);
input a;
input [31:0] b, c;
input [31:0] y;
aoi12 p [31:0] (a, b, c, y);
endmodule
module aoi12(a, b, c, y);
input a, b, c;
output y;
assign y = ~((a & b) | c);
endmodule