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verilog: add test

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This commit is contained in:
Eddie Hung 2020-03-11 06:51:03 -07:00
parent 2d63bf5877
commit 3ada82639f
1 changed files with 8 additions and 0 deletions
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tests/various/src.ys Normal file
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logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
read_verilog <<EOT
module top(input i, output o, p);
always @* o <= i;
always @* p = i;
endmodule
EOT