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Miodrag Milanovic 2026-06-23 07:17:22 +02:00
parent 1f0ac8fffc
commit 3ac58b3ac1
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138
techlibs/gatemate/arith_map.v
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@ -1,69 +1,69 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1)
begin: slice
CC_ADDF addf_i (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.CO(CO[i]),
.S(Y[i])
);
end
endgenerate
assign X = AA ^ BB;
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1)
begin: slice
CC_ADDF addf_i (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.CO(CO[i]),
.S(Y[i])
);
end
endgenerate
assign X = AA ^ BB;
endmodule

1764
techlibs/gatemate/brams_map.v
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680
techlibs/gatemate/cells_bb.v
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@ -1,340 +1,340 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOCK_REQ = 1,
parameter CLK270_DOUB = 0,
parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *) (* keep *)
module CC_SERDES #(
parameter [4:0] RX_BUF_RESET_TIME = 3,
parameter [4:0] RX_PCS_RESET_TIME = 3,
parameter [4:0] RX_RESET_TIMER_PRESC = 0,
parameter [0:0] RX_RESET_DONE_GATE = 0,
parameter [4:0] RX_CDR_RESET_TIME = 3,
parameter [4:0] RX_EQA_RESET_TIME = 3,
parameter [4:0] RX_PMA_RESET_TIME = 3,
parameter [0:0] RX_WAIT_CDR_LOCK = 1,
parameter [0:0] RX_CALIB_EN = 0,
parameter [0:0] RX_CALIB_OVR = 0,
parameter [3:0] RX_CALIB_VAL = 0,
parameter [2:0] RX_RTERM_VCMSEL = 4,
parameter [0:0] RX_RTERM_PD = 0,
parameter [7:0] RX_EQA_CKP_LF = 8'hA3,
parameter [7:0] RX_EQA_CKP_HF = 8'hA3,
parameter [7:0] RX_EQA_CKP_OFFSET = 8'h01,
parameter [0:0] RX_EN_EQA = 0,
parameter [3:0] RX_EQA_LOCK_CFG = 0,
parameter [4:0] RX_TH_MON1 = 8,
parameter [3:0] RX_EN_EQA_EXT_VALUE = 0,
parameter [4:0] RX_TH_MON2 = 8,
parameter [4:0] RX_TAPW = 8,
parameter [4:0] RX_AFE_OFFSET = 8,
parameter [15:0] RX_EQA_CONFIG = 16'h01C0,
parameter [4:0] RX_AFE_PEAK = 16,
parameter [3:0] RX_AFE_GAIN = 8,
parameter [2:0] RX_AFE_VCMSEL = 4,
parameter [7:0] RX_CDR_CKP = 8'hF8,
parameter [7:0] RX_CDR_CKI = 0,
parameter [6:0] RX_CDR_TRANS_TH = 7'h08,
parameter [7:0] RX_CDR_LOCK_CFG = 8'hD5,
parameter [14:0] RX_CDR_FREQ_ACC = 0,
parameter [15:0] RX_CDR_PHASE_ACC = 0,
parameter [1:0] RX_CDR_SET_ACC_CONFIG = 0,
parameter [0:0] RX_CDR_FORCE_LOCK = 0,
parameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,
parameter [0:0] RX_MCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_MCOMMA_ALIGN = 0,
parameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,
parameter [0:0] RX_PCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_PCOMMA_ALIGN = 0,
parameter [1:0] RX_ALIGN_COMMA_WORD = 0,
parameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,
parameter [1:0] RX_SLIDE_MODE = 0,
parameter [0:0] RX_COMMA_DETECT_EN_OVR = 0,
parameter [0:0] RX_COMMA_DETECT_EN = 0,
parameter [1:0] RX_SLIDE = 0,
parameter [0:0] RX_EYE_MEAS_EN = 0,
parameter [14:0] RX_EYE_MEAS_CFG = 0,
parameter [5:0] RX_MON_PH_OFFSET = 0,
parameter [3:0] RX_EI_BIAS = 0,
parameter [3:0] RX_EI_BW_SEL = 4,
parameter [0:0] RX_EN_EI_DETECTOR_OVR = 0,
parameter [0:0] RX_EN_EI_DETECTOR = 0,
parameter [0:0] RX_DATA_SEL = 0,
parameter [0:0] RX_BUF_BYPASS = 0,
parameter [0:0] RX_CLKCOR_USE = 0,
parameter [5:0] RX_CLKCOR_MIN_LAT = 32,
parameter [5:0] RX_CLKCOR_MAX_LAT = 39,
parameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,
parameter [0:0] RX_PMA_LOOPBACK = 0,
parameter [0:0] RX_PCS_LOOPBACK = 0,
parameter [1:0] RX_DATAPATH_SEL = 3,
parameter [0:0] RX_PRBS_OVR = 0,
parameter [2:0] RX_PRBS_SEL = 0,
parameter [0:0] RX_LOOPBACK_OVR = 0,
parameter [0:0] RX_PRBS_CNT_RESET = 0,
parameter [0:0] RX_POWER_DOWN_OVR = 0,
parameter [0:0] RX_POWER_DOWN_N = 0,
parameter [0:0] RX_RESET_OVR = 0,
parameter [0:0] RX_RESET = 0,
parameter [0:0] RX_PMA_RESET_OVR = 0,
parameter [0:0] RX_PMA_RESET = 0,
parameter [0:0] RX_EQA_RESET_OVR = 0,
parameter [0:0] RX_EQA_RESET = 0,
parameter [0:0] RX_CDR_RESET_OVR = 0,
parameter [0:0] RX_CDR_RESET = 0,
parameter [0:0] RX_PCS_RESET_OVR = 0,
parameter [0:0] RX_PCS_RESET = 0,
parameter [0:0] RX_BUF_RESET_OVR = 0,
parameter [0:0] RX_BUF_RESET = 0,
parameter [0:0] RX_POLARITY_OVR = 0,
parameter [0:0] RX_POLARITY = 0,
parameter [0:0] RX_8B10B_EN_OVR = 0,
parameter [0:0] RX_8B10B_EN = 0,
parameter [7:0] RX_8B10B_BYPASS = 0,
parameter [0:0] RX_BYTE_REALIGN = 0,
parameter [0:0] RX_DBG_EN = 0,
parameter [1:0] RX_DBG_SEL = 0,
parameter [0:0] RX_DBG_MODE = 0,
parameter [5:0] RX_DBG_SRAM_DELAY = 6'h05,
parameter [9:0] RX_DBG_ADDR = 0,
parameter [0:0] RX_DBG_RE = 0,
parameter [0:0] RX_DBG_WE = 0,
parameter [19:0] RX_DBG_DATA = 0,
parameter [4:0] TX_SEL_PRE = 0,
parameter [4:0] TX_SEL_POST = 0,
parameter [4:0] TX_AMP = 15,
parameter [4:0] TX_BRANCH_EN_PRE = 0,
parameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST = 0,
parameter [2:0] TX_TAIL_CASCODE = 4,
parameter [6:0] TX_DC_ENABLE = 63,
parameter [4:0] TX_DC_OFFSET = 0,
parameter [4:0] TX_CM_RAISE = 0,
parameter [4:0] TX_CM_THRESHOLD_0 = 14,
parameter [4:0] TX_CM_THRESHOLD_1 = 16,
parameter [4:0] TX_SEL_PRE_EI = 0,
parameter [4:0] TX_SEL_POST_EI = 0,
parameter [4:0] TX_AMP_EI = 15,
parameter [4:0] TX_BRANCH_EN_PRE_EI = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_EI = 0,
parameter [2:0] TX_TAIL_CASCODE_EI = 4,
parameter [6:0] TX_DC_ENABLE_EI = 63,
parameter [4:0] TX_DC_OFFSET_EI = 0,
parameter [4:0] TX_CM_RAISE_EI = 0,
parameter [4:0] TX_CM_THRESHOLD_0_EI = 14,
parameter [4:0] TX_CM_THRESHOLD_1_EI = 16,
parameter [4:0] TX_SEL_PRE_RXDET = 0,
parameter [4:0] TX_SEL_POST_RXDET = 0,
parameter [4:0] TX_AMP_RXDET = 15,
parameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_RXDET = 0,
parameter [2:0] TX_TAIL_CASCODE_RXDET = 4,
parameter [6:0] TX_DC_ENABLE_RXDET = 63,
parameter [4:0] TX_DC_OFFSET_RXDET = 0,
parameter [4:0] TX_CM_RAISE_RXDET = 0,
parameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14,
parameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16,
parameter [0:0] TX_CALIB_EN = 0,
parameter [0:0] TX_CALIB_OVR = 0,
parameter [3:0] TX_CALIB_VAL = 0,
parameter [7:0] TX_CM_REG_KI = 8'h80,
parameter [0:0] TX_CM_SAR_EN = 0,
parameter [0:0] TX_CM_REG_EN = 1,
parameter [4:0] TX_PMA_RESET_TIME = 3,
parameter [4:0] TX_PCS_RESET_TIME = 3,
parameter [0:0] TX_PCS_RESET_OVR = 0,
parameter [0:0] TX_PCS_RESET = 0,
parameter [0:0] TX_PMA_RESET_OVR = 0,
parameter [0:0] TX_PMA_RESET = 0,
parameter [0:0] TX_RESET_OVR = 0,
parameter [0:0] TX_RESET = 0,
parameter [1:0] TX_PMA_LOOPBACK = 0,
parameter [0:0] TX_PCS_LOOPBACK = 0,
parameter [1:0] TX_DATAPATH_SEL = 3,
parameter [0:0] TX_PRBS_OVR = 0,
parameter [2:0] TX_PRBS_SEL = 0,
parameter [0:0] TX_PRBS_FORCE_ERR = 0,
parameter [0:0] TX_LOOPBACK_OVR = 0,
parameter [0:0] TX_POWER_DOWN_OVR = 0,
parameter [0:0] TX_POWER_DOWN_N = 0,
parameter [0:0] TX_ELEC_IDLE_OVR = 0,
parameter [0:0] TX_ELEC_IDLE = 0,
parameter [0:0] TX_DETECT_RX_OVR = 0,
parameter [0:0] TX_DETECT_RX = 0,
parameter [0:0] TX_POLARITY_OVR = 0,
parameter [0:0] TX_POLARITY = 0,
parameter [0:0] TX_8B10B_EN_OVR = 0,
parameter [0:0] TX_8B10B_EN = 0,
parameter [0:0] TX_DATA_OVR = 0,
parameter [2:0] TX_DATA_CNT = 0,
parameter [0:0] TX_DATA_VALID = 0,
parameter [0:0] PLL_EN_ADPLL_CTRL = 0,
parameter [0:0] PLL_CONFIG_SEL = 0,
parameter [0:0] PLL_SET_OP_LOCK = 0,
parameter [0:0] PLL_ENFORCE_LOCK = 0,
parameter [0:0] PLL_DISABLE_LOCK = 0,
parameter [0:0] PLL_LOCK_WINDOW = 1,
parameter [0:0] PLL_FAST_LOCK = 1,
parameter [0:0] PLL_SYNC_BYPASS = 0,
parameter [0:0] PLL_PFD_SELECT = 0,
parameter [0:0] PLL_REF_BYPASS = 0,
parameter [0:0] PLL_REF_SEL = 0,
parameter [0:0] PLL_REF_RTERM = 1,
parameter [5:0] PLL_FCNTRL = 58,
parameter [5:0] PLL_MAIN_DIVSEL = 27,
parameter [1:0] PLL_OUT_DIVSEL = 0,
parameter [4:0] PLL_CI = 3,
parameter [9:0] PLL_CP = 80,
parameter [3:0] PLL_AO = 0,
parameter [2:0] PLL_SCAP = 0,
parameter [1:0] PLL_FILTER_SHIFT = 2,
parameter [2:0] PLL_SAR_LIMIT = 2,
parameter [10:0] PLL_FT = 512,
parameter [0:0] PLL_OPEN_LOOP = 0,
parameter [0:0] PLL_SCAP_AUTO_CAL = 1,
parameter [2:0] PLL_BISC_MODE = 4,
parameter [3:0] PLL_BISC_TIMER_MAX = 15,
parameter [0:0] PLL_BISC_OPT_DET_IND = 0,
parameter [0:0] PLL_BISC_PFD_SEL = 0,
parameter [0:0] PLL_BISC_DLY_DIR = 0,
parameter [2:0] PLL_BISC_COR_DLY = 1,
parameter [0:0] PLL_BISC_CAL_SIGN = 0,
parameter [0:0] PLL_BISC_CAL_AUTO = 1,
parameter [4:0] PLL_BISC_CP_MIN = 4,
parameter [4:0] PLL_BISC_CP_MAX = 18,
parameter [4:0] PLL_BISC_CP_START = 12,
parameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,
parameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,
parameter [0:0] SERDES_ENABLE = 0,
parameter [0:0] SERDES_AUTO_INIT = 0,
parameter [0:0] SERDES_TESTMODE = 0
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWER_DOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input TX_CLK_I,
input RX_CLK_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWER_DOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input REGFILE_CLK_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output TX_DETECT_RX_DONE_O,
output TX_DETECT_RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESET_DONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESET_DONE_O,
output RX_EI_EN_O,
output RX_CLK_O,
output PLL_CLK_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule
(* blackbox *) (* keep *)
module CC_USR_RSTN (
output USR_RSTN
);
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOCK_REQ = 1,
parameter CLK270_DOUB = 0,
parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *) (* keep *)
module CC_SERDES #(
parameter [4:0] RX_BUF_RESET_TIME = 3,
parameter [4:0] RX_PCS_RESET_TIME = 3,
parameter [4:0] RX_RESET_TIMER_PRESC = 0,
parameter [0:0] RX_RESET_DONE_GATE = 0,
parameter [4:0] RX_CDR_RESET_TIME = 3,
parameter [4:0] RX_EQA_RESET_TIME = 3,
parameter [4:0] RX_PMA_RESET_TIME = 3,
parameter [0:0] RX_WAIT_CDR_LOCK = 1,
parameter [0:0] RX_CALIB_EN = 0,
parameter [0:0] RX_CALIB_OVR = 0,
parameter [3:0] RX_CALIB_VAL = 0,
parameter [2:0] RX_RTERM_VCMSEL = 4,
parameter [0:0] RX_RTERM_PD = 0,
parameter [7:0] RX_EQA_CKP_LF = 8'hA3,
parameter [7:0] RX_EQA_CKP_HF = 8'hA3,
parameter [7:0] RX_EQA_CKP_OFFSET = 8'h01,
parameter [0:0] RX_EN_EQA = 0,
parameter [3:0] RX_EQA_LOCK_CFG = 0,
parameter [4:0] RX_TH_MON1 = 8,
parameter [3:0] RX_EN_EQA_EXT_VALUE = 0,
parameter [4:0] RX_TH_MON2 = 8,
parameter [4:0] RX_TAPW = 8,
parameter [4:0] RX_AFE_OFFSET = 8,
parameter [15:0] RX_EQA_CONFIG = 16'h01C0,
parameter [4:0] RX_AFE_PEAK = 16,
parameter [3:0] RX_AFE_GAIN = 8,
parameter [2:0] RX_AFE_VCMSEL = 4,
parameter [7:0] RX_CDR_CKP = 8'hF8,
parameter [7:0] RX_CDR_CKI = 0,
parameter [6:0] RX_CDR_TRANS_TH = 7'h08,
parameter [7:0] RX_CDR_LOCK_CFG = 8'hD5,
parameter [14:0] RX_CDR_FREQ_ACC = 0,
parameter [15:0] RX_CDR_PHASE_ACC = 0,
parameter [1:0] RX_CDR_SET_ACC_CONFIG = 0,
parameter [0:0] RX_CDR_FORCE_LOCK = 0,
parameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,
parameter [0:0] RX_MCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_MCOMMA_ALIGN = 0,
parameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,
parameter [0:0] RX_PCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_PCOMMA_ALIGN = 0,
parameter [1:0] RX_ALIGN_COMMA_WORD = 0,
parameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,
parameter [1:0] RX_SLIDE_MODE = 0,
parameter [0:0] RX_COMMA_DETECT_EN_OVR = 0,
parameter [0:0] RX_COMMA_DETECT_EN = 0,
parameter [1:0] RX_SLIDE = 0,
parameter [0:0] RX_EYE_MEAS_EN = 0,
parameter [14:0] RX_EYE_MEAS_CFG = 0,
parameter [5:0] RX_MON_PH_OFFSET = 0,
parameter [3:0] RX_EI_BIAS = 0,
parameter [3:0] RX_EI_BW_SEL = 4,
parameter [0:0] RX_EN_EI_DETECTOR_OVR = 0,
parameter [0:0] RX_EN_EI_DETECTOR = 0,
parameter [0:0] RX_DATA_SEL = 0,
parameter [0:0] RX_BUF_BYPASS = 0,
parameter [0:0] RX_CLKCOR_USE = 0,
parameter [5:0] RX_CLKCOR_MIN_LAT = 32,
parameter [5:0] RX_CLKCOR_MAX_LAT = 39,
parameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,
parameter [0:0] RX_PMA_LOOPBACK = 0,
parameter [0:0] RX_PCS_LOOPBACK = 0,
parameter [1:0] RX_DATAPATH_SEL = 3,
parameter [0:0] RX_PRBS_OVR = 0,
parameter [2:0] RX_PRBS_SEL = 0,
parameter [0:0] RX_LOOPBACK_OVR = 0,
parameter [0:0] RX_PRBS_CNT_RESET = 0,
parameter [0:0] RX_POWER_DOWN_OVR = 0,
parameter [0:0] RX_POWER_DOWN_N = 0,
parameter [0:0] RX_RESET_OVR = 0,
parameter [0:0] RX_RESET = 0,
parameter [0:0] RX_PMA_RESET_OVR = 0,
parameter [0:0] RX_PMA_RESET = 0,
parameter [0:0] RX_EQA_RESET_OVR = 0,
parameter [0:0] RX_EQA_RESET = 0,
parameter [0:0] RX_CDR_RESET_OVR = 0,
parameter [0:0] RX_CDR_RESET = 0,
parameter [0:0] RX_PCS_RESET_OVR = 0,
parameter [0:0] RX_PCS_RESET = 0,
parameter [0:0] RX_BUF_RESET_OVR = 0,
parameter [0:0] RX_BUF_RESET = 0,
parameter [0:0] RX_POLARITY_OVR = 0,
parameter [0:0] RX_POLARITY = 0,
parameter [0:0] RX_8B10B_EN_OVR = 0,
parameter [0:0] RX_8B10B_EN = 0,
parameter [7:0] RX_8B10B_BYPASS = 0,
parameter [0:0] RX_BYTE_REALIGN = 0,
parameter [0:0] RX_DBG_EN = 0,
parameter [1:0] RX_DBG_SEL = 0,
parameter [0:0] RX_DBG_MODE = 0,
parameter [5:0] RX_DBG_SRAM_DELAY = 6'h05,
parameter [9:0] RX_DBG_ADDR = 0,
parameter [0:0] RX_DBG_RE = 0,
parameter [0:0] RX_DBG_WE = 0,
parameter [19:0] RX_DBG_DATA = 0,
parameter [4:0] TX_SEL_PRE = 0,
parameter [4:0] TX_SEL_POST = 0,
parameter [4:0] TX_AMP = 15,
parameter [4:0] TX_BRANCH_EN_PRE = 0,
parameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST = 0,
parameter [2:0] TX_TAIL_CASCODE = 4,
parameter [6:0] TX_DC_ENABLE = 63,
parameter [4:0] TX_DC_OFFSET = 0,
parameter [4:0] TX_CM_RAISE = 0,
parameter [4:0] TX_CM_THRESHOLD_0 = 14,
parameter [4:0] TX_CM_THRESHOLD_1 = 16,
parameter [4:0] TX_SEL_PRE_EI = 0,
parameter [4:0] TX_SEL_POST_EI = 0,
parameter [4:0] TX_AMP_EI = 15,
parameter [4:0] TX_BRANCH_EN_PRE_EI = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_EI = 0,
parameter [2:0] TX_TAIL_CASCODE_EI = 4,
parameter [6:0] TX_DC_ENABLE_EI = 63,
parameter [4:0] TX_DC_OFFSET_EI = 0,
parameter [4:0] TX_CM_RAISE_EI = 0,
parameter [4:0] TX_CM_THRESHOLD_0_EI = 14,
parameter [4:0] TX_CM_THRESHOLD_1_EI = 16,
parameter [4:0] TX_SEL_PRE_RXDET = 0,
parameter [4:0] TX_SEL_POST_RXDET = 0,
parameter [4:0] TX_AMP_RXDET = 15,
parameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_RXDET = 0,
parameter [2:0] TX_TAIL_CASCODE_RXDET = 4,
parameter [6:0] TX_DC_ENABLE_RXDET = 63,
parameter [4:0] TX_DC_OFFSET_RXDET = 0,
parameter [4:0] TX_CM_RAISE_RXDET = 0,
parameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14,
parameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16,
parameter [0:0] TX_CALIB_EN = 0,
parameter [0:0] TX_CALIB_OVR = 0,
parameter [3:0] TX_CALIB_VAL = 0,
parameter [7:0] TX_CM_REG_KI = 8'h80,
parameter [0:0] TX_CM_SAR_EN = 0,
parameter [0:0] TX_CM_REG_EN = 1,
parameter [4:0] TX_PMA_RESET_TIME = 3,
parameter [4:0] TX_PCS_RESET_TIME = 3,
parameter [0:0] TX_PCS_RESET_OVR = 0,
parameter [0:0] TX_PCS_RESET = 0,
parameter [0:0] TX_PMA_RESET_OVR = 0,
parameter [0:0] TX_PMA_RESET = 0,
parameter [0:0] TX_RESET_OVR = 0,
parameter [0:0] TX_RESET = 0,
parameter [1:0] TX_PMA_LOOPBACK = 0,
parameter [0:0] TX_PCS_LOOPBACK = 0,
parameter [1:0] TX_DATAPATH_SEL = 3,
parameter [0:0] TX_PRBS_OVR = 0,
parameter [2:0] TX_PRBS_SEL = 0,
parameter [0:0] TX_PRBS_FORCE_ERR = 0,
parameter [0:0] TX_LOOPBACK_OVR = 0,
parameter [0:0] TX_POWER_DOWN_OVR = 0,
parameter [0:0] TX_POWER_DOWN_N = 0,
parameter [0:0] TX_ELEC_IDLE_OVR = 0,
parameter [0:0] TX_ELEC_IDLE = 0,
parameter [0:0] TX_DETECT_RX_OVR = 0,
parameter [0:0] TX_DETECT_RX = 0,
parameter [0:0] TX_POLARITY_OVR = 0,
parameter [0:0] TX_POLARITY = 0,
parameter [0:0] TX_8B10B_EN_OVR = 0,
parameter [0:0] TX_8B10B_EN = 0,
parameter [0:0] TX_DATA_OVR = 0,
parameter [2:0] TX_DATA_CNT = 0,
parameter [0:0] TX_DATA_VALID = 0,
parameter [0:0] PLL_EN_ADPLL_CTRL = 0,
parameter [0:0] PLL_CONFIG_SEL = 0,
parameter [0:0] PLL_SET_OP_LOCK = 0,
parameter [0:0] PLL_ENFORCE_LOCK = 0,
parameter [0:0] PLL_DISABLE_LOCK = 0,
parameter [0:0] PLL_LOCK_WINDOW = 1,
parameter [0:0] PLL_FAST_LOCK = 1,
parameter [0:0] PLL_SYNC_BYPASS = 0,
parameter [0:0] PLL_PFD_SELECT = 0,
parameter [0:0] PLL_REF_BYPASS = 0,
parameter [0:0] PLL_REF_SEL = 0,
parameter [0:0] PLL_REF_RTERM = 1,
parameter [5:0] PLL_FCNTRL = 58,
parameter [5:0] PLL_MAIN_DIVSEL = 27,
parameter [1:0] PLL_OUT_DIVSEL = 0,
parameter [4:0] PLL_CI = 3,
parameter [9:0] PLL_CP = 80,
parameter [3:0] PLL_AO = 0,
parameter [2:0] PLL_SCAP = 0,
parameter [1:0] PLL_FILTER_SHIFT = 2,
parameter [2:0] PLL_SAR_LIMIT = 2,
parameter [10:0] PLL_FT = 512,
parameter [0:0] PLL_OPEN_LOOP = 0,
parameter [0:0] PLL_SCAP_AUTO_CAL = 1,
parameter [2:0] PLL_BISC_MODE = 4,
parameter [3:0] PLL_BISC_TIMER_MAX = 15,
parameter [0:0] PLL_BISC_OPT_DET_IND = 0,
parameter [0:0] PLL_BISC_PFD_SEL = 0,
parameter [0:0] PLL_BISC_DLY_DIR = 0,
parameter [2:0] PLL_BISC_COR_DLY = 1,
parameter [0:0] PLL_BISC_CAL_SIGN = 0,
parameter [0:0] PLL_BISC_CAL_AUTO = 1,
parameter [4:0] PLL_BISC_CP_MIN = 4,
parameter [4:0] PLL_BISC_CP_MAX = 18,
parameter [4:0] PLL_BISC_CP_START = 12,
parameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,
parameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,
parameter [0:0] SERDES_ENABLE = 0,
parameter [0:0] SERDES_AUTO_INIT = 0,
parameter [0:0] SERDES_TESTMODE = 0
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWER_DOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input TX_CLK_I,
input RX_CLK_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWER_DOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input REGFILE_CLK_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output TX_DETECT_RX_DONE_O,
output TX_DETECT_RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESET_DONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESET_DONE_O,
output RX_EI_EN_O,
output RX_CLK_O,
output PLL_CLK_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule
(* blackbox *) (* keep *)
module CC_USR_RSTN (
output USR_RSTN
);
endmodule

3684
techlibs/gatemate/cells_sim.v
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90
techlibs/gatemate/lut_map.v
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@ -1,45 +1,45 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

112
techlibs/gatemate/mux_map.v
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@ -1,56 +1,56 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
CC_MX8 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.D4(E), .D5(F), .D6(G), .D7(H),
.S0(S), .S1(T), .S2(U),
.Y(Y)
);
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
CC_MX4 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.S0(S), .S1(T),
.Y(Y)
);
endmodule
/*
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(S),
.Y(Y)
);
endmodule
*/
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
CC_MX8 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.D4(E), .D5(F), .D6(G), .D7(H),
.S0(S), .S1(T), .S2(U),
.Y(Y)
);
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
CC_MX4 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.S0(S), .S1(T),
.Y(Y)
);
endmodule
/*
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(S),
.Y(Y)
);
endmodule
*/

102
techlibs/gatemate/reg_map.v
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@ -1,51 +1,51 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule

780
techlibs/gatemate/synth_gatemate.cc
View file

@ -1,390 +1,390 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthGateMatePass : public ScriptPass
{
SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_gatemate [options]\n");
log("\n");
log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module.\n");
log("\n");
log(" -vlog <file>\n");
log(" write the design to the specified verilog file. Writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). An empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis.\n");
log("\n");
log(" -scopename\n");
log(" create 'scopename' attributes when flattening the netlist.\n");
log("\n");
log(" -nobram\n");
log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
log("\n");
log(" -noaddf\n");
log(" do not use CC_ADDF full adder cells in output netlist.\n");
log("\n");
log(" -nomult\n");
log(" do not use CC_MULT multiplier cells in output netlist.\n");
log("\n");
log(" -nomx8, -nomx4\n");
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
log("\n");
log(" -luttree\n");
log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n");
log(" legacy p_r.\n");
log("\n");
log(" -dff\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -abc_new\n");
log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion.\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, vlog_file, json_file;
bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new;
void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
json_file = "";
noflatten = false;
scopename = false;
nobram = false;
noaddf = false;
nomult = false;
nomx4 = false;
nomx8 = false;
luttree = false;
dff = false;
retime = false;
noiopad = false;
noclkbuf = false;
abc_new = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
vlog_file = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
noflatten = true;
continue;
}
if (args[argidx] == "-scopename") {
scopename = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-noaddf") {
noaddf = true;
continue;
}
if (args[argidx] == "-nomult") {
nomult = true;
continue;
}
if (args[argidx] == "-nomx4") {
nomx4 = true;
continue;
}
if (args[argidx] == "-nomx8") {
nomx8 = true;
continue;
}
if (args[argidx] == "-luttree") {
luttree = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
if (args[argidx] == "-abc_new") {
abc_new = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection()) {
log_cmd_error("This command only operates on fully selected designs!\n");
}
log_header(design, "Executing SYNTH_GATEMATE pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("prepare"))
{
run("proc");
if (!noflatten) {
run("check");
std::string flatten_args = scopename ? " -scopename" : "";
run("flatten" + flatten_args);
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
run("muxpack");
run("share");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
}
if (check_label("map_mult", "(skip if '-nomult')") && !nomult)
{
run("techmap -map +/gatemate/mul_map.v");
}
if (check_label("coarse"))
{
run("alumacc");
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
{
run("memory_libmap -lib +/gatemate/brams.txt");
run("techmap -map +/gatemate/brams_map.v");
}
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
std::string techmap_args = "";
if (!noaddf) {
techmap_args += " -map +/gatemate/arith_map.v";
}
run("techmap -map +/techmap.v " + techmap_args);
run("opt -fast");
if (retime) {
run("abc -dff -D 1", "(only if -retime)");
}
}
if (check_label("map_io", "(skip if '-noiopad')") && !noiopad)
{
run("iopadmap -bits "
"-inpad CC_IBUF Y:I "
"-outpad CC_OBUF A:O "
"-toutpad CC_TOBUF ~T:A:O "
"-tinoutpad CC_IOBUF ~T:Y:A:IO"
);
run("clean");
}
if (check_label("map_regs"))
{
run("opt_clean");
run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("opt_clean");
}
if (check_label("map_muxs"))
{
std::string muxcover_args;
if (!nomx4) {
muxcover_args += stringf(" -mux4");
}
if (!nomx8) {
muxcover_args += stringf(" -mux8");
}
run("muxcover " + muxcover_args);
run("opt -full");
run("simplemap");
run("techmap -map +/gatemate/mux_map.v");
}
if (check_label("map_luts"))
{
if (luttree || help_mode) {
std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib";
if (dff) {
abc_args += " -dff";
}
if (abc_new) {
run("abc_new " + abc_args, "(with -luttree and -abc_new)");
} else {
run("abc " + abc_args, "(with -luttree, without -abc_new)");
}
run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
run("gatemate_foldinv", "(with -luttree)");
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
}
if (!luttree || help_mode) {
std::string abc_args = " -dress -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(without -luttree)");
}
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/gatemate/lut_map.v");
run("clean");
}
if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf)
{
run("clkbufmap -buf CC_BUFG O:I");
run("clean");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat -width");
run("check -noinit");
run("blackbox =A:whitebox");
}
if (check_label("vlog"))
{
run("opt_clean -purge");
if (!vlog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file));
}
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode) {
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
}
} SynthGateMatePass;
PRIVATE_NAMESPACE_END
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthGateMatePass : public ScriptPass
{
SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_gatemate [options]\n");
log("\n");
log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module.\n");
log("\n");
log(" -vlog <file>\n");
log(" write the design to the specified verilog file. Writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). An empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis.\n");
log("\n");
log(" -scopename\n");
log(" create 'scopename' attributes when flattening the netlist.\n");
log("\n");
log(" -nobram\n");
log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
log("\n");
log(" -noaddf\n");
log(" do not use CC_ADDF full adder cells in output netlist.\n");
log("\n");
log(" -nomult\n");
log(" do not use CC_MULT multiplier cells in output netlist.\n");
log("\n");
log(" -nomx8, -nomx4\n");
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
log("\n");
log(" -luttree\n");
log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n");
log(" legacy p_r.\n");
log("\n");
log(" -dff\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -abc_new\n");
log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion.\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, vlog_file, json_file;
bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new;
void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
json_file = "";
noflatten = false;
scopename = false;
nobram = false;
noaddf = false;
nomult = false;
nomx4 = false;
nomx8 = false;
luttree = false;
dff = false;
retime = false;
noiopad = false;
noclkbuf = false;
abc_new = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
vlog_file = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
noflatten = true;
continue;
}
if (args[argidx] == "-scopename") {
scopename = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-noaddf") {
noaddf = true;
continue;
}
if (args[argidx] == "-nomult") {
nomult = true;
continue;
}
if (args[argidx] == "-nomx4") {
nomx4 = true;
continue;
}
if (args[argidx] == "-nomx8") {
nomx8 = true;
continue;
}
if (args[argidx] == "-luttree") {
luttree = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
if (args[argidx] == "-abc_new") {
abc_new = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection()) {
log_cmd_error("This command only operates on fully selected designs!\n");
}
log_header(design, "Executing SYNTH_GATEMATE pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("prepare"))
{
run("proc");
if (!noflatten) {
run("check");
std::string flatten_args = scopename ? " -scopename" : "";
run("flatten" + flatten_args);
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
run("muxpack");
run("share");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
}
if (check_label("map_mult", "(skip if '-nomult')") && !nomult)
{
run("techmap -map +/gatemate/mul_map.v");
}
if (check_label("coarse"))
{
run("alumacc");
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
{
run("memory_libmap -lib +/gatemate/brams.txt");
run("techmap -map +/gatemate/brams_map.v");
}
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
std::string techmap_args = "";
if (!noaddf) {
techmap_args += " -map +/gatemate/arith_map.v";
}
run("techmap -map +/techmap.v " + techmap_args);
run("opt -fast");
if (retime) {
run("abc -dff -D 1", "(only if -retime)");
}
}
if (check_label("map_io", "(skip if '-noiopad')") && !noiopad)
{
run("iopadmap -bits "
"-inpad CC_IBUF Y:I "
"-outpad CC_OBUF A:O "
"-toutpad CC_TOBUF ~T:A:O "
"-tinoutpad CC_IOBUF ~T:Y:A:IO"
);
run("clean");
}
if (check_label("map_regs"))
{
run("opt_clean");
run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("opt_clean");
}
if (check_label("map_muxs"))
{
std::string muxcover_args;
if (!nomx4) {
muxcover_args += stringf(" -mux4");
}
if (!nomx8) {
muxcover_args += stringf(" -mux8");
}
run("muxcover " + muxcover_args);
run("opt -full");
run("simplemap");
run("techmap -map +/gatemate/mux_map.v");
}
if (check_label("map_luts"))
{
if (luttree || help_mode) {
std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib";
if (dff) {
abc_args += " -dff";
}
if (abc_new) {
run("abc_new " + abc_args, "(with -luttree and -abc_new)");
} else {
run("abc " + abc_args, "(with -luttree, without -abc_new)");
}
run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
run("gatemate_foldinv", "(with -luttree)");
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
}
if (!luttree || help_mode) {
std::string abc_args = " -dress -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(without -luttree)");
}
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/gatemate/lut_map.v");
run("clean");
}
if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf)
{
run("clkbufmap -buf CC_BUFG O:I");
run("clean");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat -width");
run("check -noinit");
run("blackbox =A:whitebox");
}
if (check_label("vlog"))
{
run("opt_clean -purge");
if (!vlog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file));
}
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode) {
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
}
} SynthGateMatePass;
PRIVATE_NAMESPACE_END