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Consistent use of 'override' for virtual methods in derived classes.

Browse source 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
This commit is contained in:
Henner Zeller 2018-07-20 23:41:18 -07:00
parent 323f6f6f60
commit 3aa4484a3c
170 changed files with 414 additions and 416 deletions
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8
techlibs/achronix/synth_achronix.cc
View file

@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthAchronixPass : public ScriptPass {
SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -63,7 +63,7 @@ struct SynthAchronixPass : public ScriptPass {
string top_opt, family_opt, vout_file;
bool retime, flatten;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
vout_file = "";
@ -71,7 +71,7 @@ struct SynthAchronixPass : public ScriptPass {
flatten = true;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -118,7 +118,7 @@ struct SynthAchronixPass : public ScriptPass {
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

8
techlibs/common/prep.cc
View file

@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass
{
PrepPass() : ScriptPass("prep", "generic synthesis script") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass
string top_module, fsm_opts;
bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_module.clear();
@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass
nordff = true;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))

8
techlibs/common/synth.cc
View file

@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass
{
SynthPass() : ScriptPass("synth", "generic synthesis script") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -81,7 +81,7 @@ struct SynthPass : public ScriptPass
string top_module, fsm_opts, memory_opts;
bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_module.clear();
fsm_opts.clear();
@ -95,7 +95,7 @@ struct SynthPass : public ScriptPass
noshare = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -165,7 +165,7 @@ struct SynthPass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

4
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Coolrunner2SopPass : public Pass {
Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
virtual void help()
void help() YS_OVERRIDE
{
log("\n");
log(" coolrunner2_sop [options] [selection]\n");
@ -33,7 +33,7 @@ struct Coolrunner2SopPass : public Pass {
log("Break $sop cells into ANDTERM/ORTERM cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
extra_args(args, 1, design);

8
techlibs/coolrunner2/synth_coolrunner2.cc
View file

@ -29,7 +29,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
{
SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -66,7 +66,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
string top_opt, json_file;
bool flatten, retime;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
json_file = "";
@ -74,7 +74,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
retime = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -121,7 +121,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

8
techlibs/easic/synth_easic.cc
View file

@ -29,7 +29,7 @@ struct SynthEasicPass : public ScriptPass
{
SynthEasicPass() : ScriptPass("synth_easic", "synthesis for eASIC platform") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -67,7 +67,7 @@ struct SynthEasicPass : public ScriptPass
string top_opt, vlog_file, etools_path;
bool flatten, retime;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
vlog_file = "";
@ -76,7 +76,7 @@ struct SynthEasicPass : public ScriptPass
retime = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -127,7 +127,7 @@ struct SynthEasicPass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str());
string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str());

8
techlibs/ecp5/synth_ecp5.cc
View file

@ -30,7 +30,7 @@ struct SynthEcp5Pass : public ScriptPass
{
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -95,7 +95,7 @@ struct SynthEcp5Pass : public ScriptPass
string top_opt, blif_file, edif_file, json_file;
bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
blif_file = "";
@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass
vpr = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -199,7 +199,7 @@ struct SynthEcp5Pass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

8
techlibs/gowin/synth_gowin.cc
View file

@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
{
SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -61,14 +61,14 @@ struct SynthGowinPass : public ScriptPass
string top_opt, vout_file;
bool retime;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
vout_file = "";
retime = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -111,7 +111,7 @@ struct SynthGowinPass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

4
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -91,7 +91,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
struct Greenpak4DffInvPass : public Pass {
Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
virtual void help()
void help() YS_OVERRIDE
{
log("\n");
log(" greenpak4_dffinv [options] [selection]\n");
@ -99,7 +99,7 @@ struct Greenpak4DffInvPass : public Pass {
log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");

8
techlibs/greenpak4/synth_greenpak4.cc
View file

@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
{
SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
string top_opt, part, json_file;
bool flatten, retime;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
part = "SLG46621V";
@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
retime = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

4
techlibs/ice40/ice40_ffinit.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfinitPass : public Pass {
Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
virtual void help()
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass {
log("nonzero init values.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");

4
techlibs/ice40/ice40_ffssr.cc
View file

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfssrPass : public Pass {
Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
virtual void help()
void help() YS_OVERRIDE
{
log("\n");
log(" ice40_ffssr [options] [selection]\n");
@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass {
log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");

4
techlibs/ice40/ice40_opt.cc
View file

@ -136,7 +136,7 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
struct Ice40OptPass : public Pass {
Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
virtual void help()
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -156,7 +156,7 @@ struct Ice40OptPass : public Pass {
log("mapped SB_LUT4 cells back to logic.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string opt_expr_args = "-mux_undef -undriven";
bool unlut_mode = false;

8
techlibs/ice40/synth_ice40.cc
View file

@ -29,7 +29,7 @@ struct SynthIce40Pass : public ScriptPass
{
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -88,7 +88,7 @@ struct SynthIce40Pass : public ScriptPass
string top_opt, blif_file, edif_file, json_file;
bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
blif_file = "";
@ -103,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
vpr = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -182,7 +182,7 @@ struct SynthIce40Pass : public ScriptPass
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{

12
techlibs/intel/synth_intel.cc
View file

@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass {
SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
virtual void help() YS_OVERRIDE
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass {
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram, noiopads;
virtual void clear_flags() YS_OVERRIDE
void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
family_opt = "max10";
@ -91,7 +91,7 @@ struct SynthIntelPass : public ScriptPass {
noiopads = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@ -156,7 +156,7 @@ struct SynthIntelPass : public ScriptPass {
log_pop();
}
virtual void script() YS_OVERRIDE
void script() YS_OVERRIDE
{
if (check_label("begin"))
{
@ -255,7 +255,7 @@ struct SynthIntelPass : public ScriptPass {
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
if (check_label("vpr"))
{
if (!blif_file.empty() || help_mode)
@ -264,7 +264,7 @@ struct SynthIntelPass : public ScriptPass {
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
}
}
}
}
} SynthIntelPass;
PRIVATE_NAMESPACE_END

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -38,7 +38,7 @@ struct SynthXilinxPass : public Pass
{
SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
virtual void help()
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -128,7 +128,7 @@ struct SynthXilinxPass : public Pass
log(" write_blif <file-name>\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
std::string top_opt = "-auto-top";
std::string edif_file;