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sigspec: no hash

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This commit is contained in:
Emil J. Tywoniak 2024-07-24 10:34:54 +02:00
parent 6e3bf76ea4
commit 3a7136f462
2 changed files with 17 additions and 50 deletions
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52
kernel/rtlil.cc
View file

@ -3789,7 +3789,6 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
cover("kernel.rtlil.sigspec.init.list"); cover("kernel.rtlil.sigspec.init.list");
width_ = 0; width_ = 0;
hash_ = 0;
packed_ = true; packed_ = true;
(void)new (&this->chunks_) std::vector<SigChunk>(); (void)new (&this->chunks_) std::vector<SigChunk>();
@ -3812,7 +3811,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3828,7 +3826,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Const &&value)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3844,7 +3841,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3860,7 +3856,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3876,7 +3871,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3892,7 +3886,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3908,7 +3901,6 @@ RTLIL::SigSpec::SigSpec(const std::string &str)
} else { } else {
width_ = 0; width_ = 0;
} }
hash_ = 0;
check(); check();
} }
@ -3921,7 +3913,6 @@ RTLIL::SigSpec::SigSpec(int val, int width)
if (width != 0) if (width != 0)
chunks_.emplace_back(val, width); chunks_.emplace_back(val, width);
width_ = width; width_ = width;
hash_ = 0;
check(); check();
} }
@ -3934,7 +3925,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
if (width != 0) if (width != 0)
chunks_.emplace_back(bit, width); chunks_.emplace_back(bit, width);
width_ = width; width_ = width;
hash_ = 0;
check(); check();
} }
@ -3952,7 +3942,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
chunks_.push_back(bit); chunks_.push_back(bit);
} }
width_ = width; width_ = width;
hash_ = 0;
check(); check();
} }
@ -3963,7 +3952,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
packed_ = true; packed_ = true;
(void)new (&this->chunks_) std::vector<SigChunk>(); (void)new (&this->chunks_) std::vector<SigChunk>();
width_ = 0; width_ = 0;
hash_ = 0;
for (const auto &c : chunks) for (const auto &c : chunks)
append(c); append(c);
check(); check();
@ -3976,7 +3964,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
packed_ = false; packed_ = false;
(void)new (&this->bits_) std::vector<SigBit>(); (void)new (&this->bits_) std::vector<SigBit>();
width_ = 0; width_ = 0;
hash_ = 0;
for (const auto &bit : bits) for (const auto &bit : bits)
append(bit); append(bit);
check(); check();
@ -3989,7 +3976,6 @@ RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
packed_ = false; packed_ = false;
(void)new (&this->bits_) std::vector<SigBit>(); (void)new (&this->bits_) std::vector<SigBit>();
width_ = 0; width_ = 0;
hash_ = 0;
for (const auto &bit : bits) for (const auto &bit : bits)
append(bit); append(bit);
check(); check();
@ -4002,7 +3988,6 @@ RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
packed_ = false; packed_ = false;
(void)new (&this->bits_) std::vector<SigBit>(); (void)new (&this->bits_) std::vector<SigBit>();
width_ = 0; width_ = 0;
hash_ = 0;
for (const auto &bit : bits) for (const auto &bit : bits)
append(bit); append(bit);
check(); check();
@ -4015,7 +4000,6 @@ RTLIL::SigSpec::SigSpec(bool bit)
packed_ = false; packed_ = false;
(void)new (&this->bits_) std::vector<SigBit>(); (void)new (&this->bits_) std::vector<SigBit>();
width_ = 0; width_ = 0;
hash_ = 0;
append(SigBit(bit)); append(SigBit(bit));
check(); check();
} }
@ -4097,34 +4081,32 @@ void RTLIL::SigSpec::unpack() const
new_bits.emplace_back(c, i); new_bits.emplace_back(c, i);
that->chunks_.clear(); that->chunks_.clear();
that->hash_ = 0;
that->switch_to_unpacked(); that->switch_to_unpacked();
that->bits_.swap(new_bits); that->bits_.swap(new_bits);
} }
void RTLIL::SigSpec::updhash() const size_t RTLIL::SigSpec::hash() const
{ {
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
if (that->hash_ != 0)
return;
cover("kernel.rtlil.sigspec.hash"); cover("kernel.rtlil.sigspec.hash");
that->pack(); that->pack();
that->hash_ = mkhash_init; long hash_ = mkhash_init;
for (auto &c : that->chunks_) for (auto &c : that->chunks_)
if (c.wire == NULL) { if (c.wire == NULL) {
for (auto &v : c.data) for (auto &v : c.data)
that->hash_ = mkhash(that->hash_, v); hash_ = mkhash(hash_, v);
} else { } else {
that->hash_ = mkhash(that->hash_, c.wire->name.index_); hash_ = mkhash(hash_, c.wire->name.index_);
that->hash_ = mkhash(that->hash_, c.offset); hash_ = mkhash(hash_, c.offset);
that->hash_ = mkhash(that->hash_, c.width); hash_ = mkhash(hash_, c.width);
} }
if (that->hash_ == 0) if (hash_ == 0)
that->hash_ = 1; hash_ = 1;
return hash_;
} }
void RTLIL::SigSpec::sort() void RTLIL::SigSpec::sort()
@ -4710,11 +4692,8 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
if (chunks_.size() != other.chunks_.size()) if (chunks_.size() != other.chunks_.size())
return chunks_.size() < other.chunks_.size(); return chunks_.size() < other.chunks_.size();
updhash(); if (hash() != other.hash())
other.updhash(); return hash() < other.hash();
if (hash_ != other.hash_)
return hash_ < other.hash_;
for (size_t i = 0; i < chunks_.size(); i++) for (size_t i = 0; i < chunks_.size(); i++)
if (chunks_[i] != other.chunks_[i]) { if (chunks_[i] != other.chunks_[i]) {
@ -4748,11 +4727,8 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
if (chunks_.size() != other.chunks_.size()) if (chunks_.size() != other.chunks_.size())
return false; return false;
updhash(); if (hash() != other.hash())
other.updhash(); return hash() == other.hash();
if (hash_ != other.hash_)
return false;
for (size_t i = 0; i < chunks_.size(); i++) for (size_t i = 0; i < chunks_.size(); i++)
if (chunks_[i] != other.chunks_[i]) { if (chunks_[i] != other.chunks_[i]) {

15
kernel/rtlil.h
View file

@ -843,7 +843,7 @@ struct RTLIL::SigSpec
private: private:
int width_; int width_;
bool packed_; bool packed_;
unsigned long hash_; // unsigned long hash_;
union { union {
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0 std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
std::vector<RTLIL::SigBit> bits_; // LSB at index 0 std::vector<RTLIL::SigBit> bits_; // LSB at index 0
@ -853,7 +853,6 @@ private:
void unpack() const; void unpack() const;
void switch_to_packed() const; void switch_to_packed() const;
void switch_to_unpacked() const; void switch_to_unpacked() const;
void updhash() const;
inline bool packed() const { inline bool packed() const {
return packed_; return packed_;
@ -869,14 +868,13 @@ private:
friend struct RTLIL::Module; friend struct RTLIL::Module;
public: public:
SigSpec() : width_(0), packed_(true), hash_(0), chunks_() {} SigSpec() : width_(0), packed_(true), chunks_() {}
~SigSpec() { if (packed_) chunks_.~vector(); else bits_.~vector(); } ~SigSpec() { if (packed_) chunks_.~vector(); else bits_.~vector(); }
SigSpec(std::initializer_list<RTLIL::SigSpec> parts); SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
SigSpec(const Yosys::RTLIL::SigSpec &other) SigSpec(const Yosys::RTLIL::SigSpec &other)
{ {
packed_ = other.packed_; packed_ = other.packed_;
width_ = other.width_; width_ = other.width_;
hash_ = other.hash_;
if (packed_) { if (packed_) {
(void)new (&this->chunks_) std::vector<SigChunk>(); (void)new (&this->chunks_) std::vector<SigChunk>();
chunks_ = other.chunks_; chunks_ = other.chunks_;
@ -906,7 +904,6 @@ public:
} }
width_ = other.width_; width_ = other.width_;
hash_ = other.hash_;
check(); check();
return *this; return *this;
} }
@ -927,11 +924,7 @@ public:
SigSpec(const std::set<RTLIL::SigBit> &bits); SigSpec(const std::set<RTLIL::SigBit> &bits);
explicit SigSpec(bool bit); explicit SigSpec(bool bit);
size_t get_hash() const { size_t hash() const;
if (!hash_) hash();
return hash_;
}
inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; } inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; } inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
@ -1038,8 +1031,6 @@ public:
operator std::vector<RTLIL::SigBit>() const { return bits(); } operator std::vector<RTLIL::SigBit>() const { return bits(); }
const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; } const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
unsigned int hash() const { if (!hash_) updhash(); return hash_; };
#ifndef NDEBUG #ifndef NDEBUG
void check(Module *mod = nullptr) const; void check(Module *mod = nullptr) const;
#else #else