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https://github.com/YosysHQ/yosys
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sigspec: no hash
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parent
6e3bf76ea4
commit
3a7136f462
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@ -3789,7 +3789,6 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
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cover("kernel.rtlil.sigspec.init.list");
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width_ = 0;
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hash_ = 0;
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packed_ = true;
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(void)new (&this->chunks_) std::vector<SigChunk>();
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@ -3812,7 +3811,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3828,7 +3826,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Const &&value)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3844,7 +3841,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3860,7 +3856,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3876,7 +3871,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3892,7 +3886,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3908,7 +3901,6 @@ RTLIL::SigSpec::SigSpec(const std::string &str)
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} else {
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width_ = 0;
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}
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hash_ = 0;
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check();
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}
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@ -3921,7 +3913,6 @@ RTLIL::SigSpec::SigSpec(int val, int width)
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if (width != 0)
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chunks_.emplace_back(val, width);
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width_ = width;
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hash_ = 0;
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check();
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}
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@ -3934,7 +3925,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
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if (width != 0)
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chunks_.emplace_back(bit, width);
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width_ = width;
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hash_ = 0;
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check();
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}
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@ -3952,7 +3942,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
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chunks_.push_back(bit);
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}
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width_ = width;
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hash_ = 0;
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check();
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}
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@ -3963,7 +3952,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
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packed_ = true;
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(void)new (&this->chunks_) std::vector<SigChunk>();
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width_ = 0;
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hash_ = 0;
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for (const auto &c : chunks)
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append(c);
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check();
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@ -3976,7 +3964,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
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packed_ = false;
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(void)new (&this->bits_) std::vector<SigBit>();
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width_ = 0;
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hash_ = 0;
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for (const auto &bit : bits)
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append(bit);
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check();
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@ -3989,7 +3976,6 @@ RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
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packed_ = false;
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(void)new (&this->bits_) std::vector<SigBit>();
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width_ = 0;
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hash_ = 0;
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for (const auto &bit : bits)
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append(bit);
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check();
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@ -4002,7 +3988,6 @@ RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
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packed_ = false;
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(void)new (&this->bits_) std::vector<SigBit>();
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width_ = 0;
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hash_ = 0;
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for (const auto &bit : bits)
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append(bit);
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check();
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@ -4015,7 +4000,6 @@ RTLIL::SigSpec::SigSpec(bool bit)
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packed_ = false;
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(void)new (&this->bits_) std::vector<SigBit>();
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width_ = 0;
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hash_ = 0;
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append(SigBit(bit));
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check();
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}
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@ -4097,34 +4081,32 @@ void RTLIL::SigSpec::unpack() const
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new_bits.emplace_back(c, i);
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that->chunks_.clear();
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that->hash_ = 0;
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that->switch_to_unpacked();
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that->bits_.swap(new_bits);
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}
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void RTLIL::SigSpec::updhash() const
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size_t RTLIL::SigSpec::hash() const
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{
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RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
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if (that->hash_ != 0)
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return;
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cover("kernel.rtlil.sigspec.hash");
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that->pack();
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that->hash_ = mkhash_init;
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long hash_ = mkhash_init;
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for (auto &c : that->chunks_)
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if (c.wire == NULL) {
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for (auto &v : c.data)
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that->hash_ = mkhash(that->hash_, v);
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hash_ = mkhash(hash_, v);
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} else {
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that->hash_ = mkhash(that->hash_, c.wire->name.index_);
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that->hash_ = mkhash(that->hash_, c.offset);
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that->hash_ = mkhash(that->hash_, c.width);
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hash_ = mkhash(hash_, c.wire->name.index_);
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hash_ = mkhash(hash_, c.offset);
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hash_ = mkhash(hash_, c.width);
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}
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if (that->hash_ == 0)
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that->hash_ = 1;
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if (hash_ == 0)
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hash_ = 1;
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return hash_;
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}
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void RTLIL::SigSpec::sort()
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@ -4710,11 +4692,8 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
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if (chunks_.size() != other.chunks_.size())
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return chunks_.size() < other.chunks_.size();
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updhash();
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other.updhash();
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if (hash_ != other.hash_)
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return hash_ < other.hash_;
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if (hash() != other.hash())
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return hash() < other.hash();
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for (size_t i = 0; i < chunks_.size(); i++)
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if (chunks_[i] != other.chunks_[i]) {
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@ -4748,11 +4727,8 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
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if (chunks_.size() != other.chunks_.size())
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return false;
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updhash();
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other.updhash();
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if (hash_ != other.hash_)
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return false;
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if (hash() != other.hash())
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return hash() == other.hash();
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for (size_t i = 0; i < chunks_.size(); i++)
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if (chunks_[i] != other.chunks_[i]) {
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@ -843,7 +843,7 @@ struct RTLIL::SigSpec
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private:
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int width_;
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bool packed_;
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unsigned long hash_;
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// unsigned long hash_;
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union {
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std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
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std::vector<RTLIL::SigBit> bits_; // LSB at index 0
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@ -853,7 +853,6 @@ private:
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void unpack() const;
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void switch_to_packed() const;
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void switch_to_unpacked() const;
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void updhash() const;
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inline bool packed() const {
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return packed_;
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@ -869,14 +868,13 @@ private:
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friend struct RTLIL::Module;
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public:
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SigSpec() : width_(0), packed_(true), hash_(0), chunks_() {}
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SigSpec() : width_(0), packed_(true), chunks_() {}
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~SigSpec() { if (packed_) chunks_.~vector(); else bits_.~vector(); }
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SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
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SigSpec(const Yosys::RTLIL::SigSpec &other)
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{
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packed_ = other.packed_;
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width_ = other.width_;
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hash_ = other.hash_;
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if (packed_) {
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(void)new (&this->chunks_) std::vector<SigChunk>();
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chunks_ = other.chunks_;
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@ -906,7 +904,6 @@ public:
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}
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width_ = other.width_;
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hash_ = other.hash_;
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check();
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return *this;
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}
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@ -927,11 +924,7 @@ public:
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SigSpec(const std::set<RTLIL::SigBit> &bits);
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explicit SigSpec(bool bit);
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size_t get_hash() const {
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if (!hash_) hash();
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return hash_;
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}
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size_t hash() const;
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inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
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inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
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@ -1038,8 +1031,6 @@ public:
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operator std::vector<RTLIL::SigBit>() const { return bits(); }
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const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
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unsigned int hash() const { if (!hash_) updhash(); return hash_; };
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#ifndef NDEBUG
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void check(Module *mod = nullptr) const;
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#else
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