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twine: avoid TwinePool::lookup

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 22:57:13 +02:00
parent 4061593ce5
commit 3a5f5c77bf
23 changed files with 277 additions and 259 deletions
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2
passes/opt/opt_clean/cells_all.cc
View file

@ -326,7 +326,7 @@ void remove_mems(RTLIL::Module* mod, const MemAnalysis& mem_analysis, bool verbo
if (!mem_analysis.unused[it.second].load(std::memory_order_relaxed))
continue;
std::string id_s = it.first;
TwineRef id = mod->design->twines.add(Twine{it.first});
TwineRef id = mod->design->twines.add(std::string{it.first});
if (verbose)
log_debug(" removing unused memory `%s'.\n", id_s);
delete mod->memories.at(id);

11
passes/opt/opt_clean/wires.cc
View file

@ -144,12 +144,11 @@ bool compare_signals(const RTLIL::SigBit &s1, const RTLIL::SigBit &s2, const Sha
return w2->name.lt_by_name(w1->name);
}
bool check_public_name(RTLIL::IdString id)
bool check_public_name(const std::string &id_str)
{
if (id.begins_with("$"))
if (!id_str.empty() && id_str[0] == '$')
return false;
const std::string &id_str = id.str();
if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
if (id_str.rfind("\\_", 0) == 0 && (id_str.back() == '_' || id_str.find("_[") != std::string::npos))
return false;
if (id_str.find(".$") != std::string::npos)
return false;
@ -438,7 +437,7 @@ struct WireDeleter {
if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires
} else
if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
if (!purge_mode && check_public_name(wire->name.escaped()) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
} else
if (!check_any(used_sig_analysis.raw_connected, s1)) {
@ -520,7 +519,7 @@ struct WireDeleter {
int delete_wires(RTLIL::Module* mod, bool verbose) {
int deleted_and_unreported = 0;
for (auto wire : del_wires_queue) {
if (ys_debug() || (check_public_name(wire->name) && verbose))
if (ys_debug() || (check_public_name(wire->name.escaped()) && verbose))
log_debug(" removing unused non-port wire %s.\n", wire->name);
else
deleted_and_unreported++;

2
passes/opt/opt_expr.cc
View file

@ -421,7 +421,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, TwineRe
twines.unescaped_str(port), cell->type.unescaped(), cell, cell->module,
log_signal(sig), log_signal(new_sig));
cell->setPort(port, new_sig);
cell->type_impl = cell->module->design->twines.add(Twine{cell->type == type1 ? type2 : type1});
cell->type_impl = cell->module->design->twines.add(std::string{cell->type == type1 ? type2 : type1});
}
}
}

2
passes/opt/rmports.cc
View file

@ -77,7 +77,7 @@ struct RmportsPassPass : public Pass {
{
log(" Removing port \"%s\" from instance \"%s\"\n",
p.c_str(), cell->type);
cell->unsetPort(cell->module->design->twines.add(Twine{p.str()}));
cell->unsetPort(cell->module->design->twines.add(std::string{p.str()}));
}
}
}

8
passes/opt/wreduce.cc
View file

@ -244,7 +244,7 @@ struct WreduceWorker
{
port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
auto &twines = cell->module->design->twines;
SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
SigSpec sig = mi.sigmap(cell->getPort(twines.add(std::string{stringf("\\%c", port)})));
if (port == 'B' && cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr)))
port_signed = false;
@ -268,8 +268,8 @@ struct WreduceWorker
if (bits_removed) {
log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescaped());
// SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
cell->setPort(twines.add(Twine{stringf("\\%c", port)}), sig);
// SigSpec sig = mi.sigmap(cell->getPort(twines.add(std::string{stringf("\\%c", port)})));
cell->setPort(twines.add(std::string{stringf("\\%c", port)}), sig);
did_something = true;
}
}
@ -640,7 +640,7 @@ struct WreducePass : public Pass {
if (!opt_memx && c->type.in(TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2), TW($meminit), TW($meminit_v2))) {
std::string memid_s = c->getParam(ID::MEMID).decode_string();
TwineRef memid = design->twines.add(Twine{memid_s});
TwineRef memid = design->twines.add(std::string{memid_s});
RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) {
int cur_addrbits = c->getParam(ID::ABITS).as_int();