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twine: avoid TwinePool::lookup

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 22:57:13 +02:00
parent 4061593ce5
commit 3a5f5c77bf
23 changed files with 277 additions and 259 deletions
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29
passes/cmds/design.cc
View file

@ -254,21 +254,22 @@ struct DesignPass : public Pass {
if (import_mode)
{
std::string prefix = RTLIL::escape_id(as_name);
TwineRef as_name_ref = copy_to_design->twines.add(std::string{prefix});
pool<Module*> queue;
dict<IdString, IdString> done;
if (copy_to_design->module(prefix) != nullptr)
copy_to_design->remove(copy_to_design->module(prefix));
if (copy_to_design->module(as_name_ref) != nullptr)
copy_to_design->remove(copy_to_design->module(as_name_ref));
if (GetSize(copy_src_modules) != 1)
log_cmd_error("No top module found in source design.\n");
for (auto mod : copy_src_modules)
{
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
log("Importing %s as %s.\n", mod, design->twines.unescaped_str(as_name_ref));
RTLIL::Module *t = mod->clone(copy_to_design, copy_to_design->twines.add(Twine{prefix}));
RTLIL::Module *t = mod->clone(copy_to_design, as_name_ref);
t->attributes.erase(ID::top);
queue.insert(t);
@ -290,21 +291,22 @@ struct DesignPass : public Pass {
if (done.count(cell->type) == 0)
{
std::string trg_name = prefix + "." + (cell->type.unescape());
std::string trg_name = prefix + "." + cell->type.unescape();
TwineRef trg_ref = copy_to_design->twines.add(std::string{trg_name});
log("Importing %s as %s.\n", fmod, RTLIL::unescape_id(trg_name));
log("Importing %s as %s.\n", log_id(fmod), RTLIL::unescape_id(trg_name).c_str());
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
if (copy_to_design->module(trg_ref) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_ref));
RTLIL::Module *t = fmod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
RTLIL::Module *t = fmod->clone(copy_to_design, trg_ref);
t->attributes.erase(ID::top);
queue.insert(t);
done[cell->type] = trg_name;
}
cell->type_impl = cell->module->design->twines.add(Twine{done.at(cell->type).str()});
cell->type_impl = cell->module->design->twines.add(std::string{done.at(cell->type).str()});
}
}
}
@ -317,11 +319,12 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules)
{
std::string trg_name = as_name.empty() ? copy_from_design->twines.str(mod->meta_->name) : RTLIL::escape_id(as_name);
TwineRef trg_ref = copy_to_design->twines.add(std::string{trg_name});
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
if (copy_to_design->module(trg_ref) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_ref));
mod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
mod->clone(copy_to_design, trg_ref);
}
}

32
passes/cmds/select.cc
View file

@ -273,7 +273,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{
if (design->module(cell->type_impl) == nullptr)
continue;
lhs.selected_modules.insert(design->twines.add(Twine{cell->type.str()}));
lhs.selected_modules.insert(design->twines.add(std::string{cell->type.str()}));
}
}
}
@ -286,7 +286,7 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &
if (lhs.selected_module(mod->meta_->name))
for (auto cell : mod->cells())
if (lhs.selected_member(mod->meta_->name, cell->meta_->name) && (design->module(cell->type_impl) != nullptr))
new_sel.selected_modules.insert(design->twines.add(Twine{cell->type.str()}));
new_sel.selected_modules.insert(design->twines.add(std::string{cell->type.str()}));
lhs = new_sel;
}
@ -295,7 +295,7 @@ static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &l
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
for (auto mod : design->modules())
for (auto cell : mod->cells())
if ((design->module(cell->type_impl) != nullptr) && lhs.selected_whole_module(design->twines.add(Twine{cell->type.str()})))
if ((design->module(cell->type_impl) != nullptr) && lhs.selected_whole_module(design->twines.add(std::string{cell->type.str()})))
new_sel.selected_members[mod->meta_->name].insert(cell->meta_->name);
lhs = new_sel;
}
@ -1480,7 +1480,7 @@ struct SelectPass : public Pass {
}
IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
IdString obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
sel.selected_members[design->twines.add(Twine{mod_name.str()})].insert(design->twines.add(Twine{obj_name.str()}));
sel.selected_members[design->twines.add(std::string{mod_name.str()})].insert(design->twines.add(std::string{obj_name.str()}));
}
select_filter_active_mod(design, sel);
@ -1745,6 +1745,7 @@ struct CdPass : public Pass {
design->push_full_selection();
design->selected_active_module = TwineRef{};
TwineSearch search(&design->twines);
while (1)
{
size_t pos = modname.rfind('.');
@ -1753,12 +1754,13 @@ struct CdPass : public Pass {
break;
modname = modname.substr(0, pos);
Module *mod = design->module(RTLIL::IdString(modname));
TwineRef mod_ref = search.find(modname);
Module *mod = design->module(mod_ref);
if (mod == nullptr)
continue;
design->selected_active_module = design->twines.add(Twine{modname});
design->selected_active_module = mod_ref;
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
@ -1769,17 +1771,18 @@ struct CdPass : public Pass {
return;
}
std::string modname = RTLIL::escape_id(args[1]);
TwineSearch search(&design->twines);
TwineRef modname = search.find(RTLIL::escape_id(args[1]));
if (design->module(RTLIL::IdString(modname)) == nullptr && design->selected_active_module) {
if (design->module(modname) == nullptr && design->selected_active_module) {
RTLIL::Module *module = design->module(design->selected_active_module);
TwineRef cell_ref = design->twines.lookup(modname);
TwineRef cell_ref = modname;
if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
modname = design->twines.str(module->cell(cell_ref)->type.ref());
modname = module->cell(cell_ref)->type_impl;
}
if (design->module(RTLIL::IdString(modname)) != nullptr) {
design->selected_active_module = design->twines.add(Twine{modname});
if (design->module(modname) != nullptr) {
design->selected_active_module = modname;
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
@ -1787,7 +1790,7 @@ struct CdPass : public Pass {
return;
}
log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname));
log_cmd_error("No such module `%s' found!\n", design->twines.str(modname));
}
} CdPass;
@ -1844,8 +1847,9 @@ struct LsPass : public Pass {
if (!matches.empty()) {
log("\n%d %s:\n", int(matches.size()), "modules");
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
TwineSearch search(&design->twines);
for (auto id : matches)
log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(id)) ? "" : "*");
log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(search.find(id.str()))) ? "" : "*");
}
}
else

7
passes/cmds/show.cc
View file

@ -56,6 +56,7 @@ struct ShowWorker
FILE *f;
RTLIL::Design *design;
TwineSearch search;
RTLIL::Module *module;
uint32_t currentColor;
bool genWidthLabels;
@ -148,7 +149,7 @@ struct ShowWorker
std::string findColor(IdString member_name)
{
TwineRef member_ref = design->twines.lookup(member_name.str());
TwineRef member_ref = search.find(member_name.str());
for (auto &s : color_selections)
if (member_ref && s.second.selected_member(module->meta_->name, member_ref)) {
return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
@ -175,7 +176,7 @@ struct ShowWorker
const char *findLabel(std::string member_name)
{
TwineRef member_ref = design->twines.lookup(member_name);
TwineRef member_ref = search.find(member_name);
for (auto &s : label_selections)
if (member_ref && s.second.selected_member(module->meta_->name, member_ref))
return escape(s.first);
@ -627,7 +628,7 @@ struct ShowWorker
const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::IdString colorattr) :
f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
f(f), design(design), search(&design->twines), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
{

10
passes/cmds/stat.cc
View file

@ -261,7 +261,7 @@ struct statdata_t {
} else if (it == "S") {
port_name = TW::S;
} else {
port_name = design->twines.add(Twine{it});
port_name = design->twines.add(std::string{it});
}
if (cell->hasPort(port_name)) {
int width = GetSize(cell->getPort(port_name));
@ -886,7 +886,7 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
if (ar != nullptr && !ar->value.empty()) {
string prefix = cell->args[0].substr(0, 1) == "$" ? "" : "\\";
// TwineRef t = twines.add(Twine{prefix + cell->args[0]});
// TwineRef t = twines.add(std::string{prefix + cell->args[0]});
IdString t = prefix + cell->args[0];
cell_area[t] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
port_names};
@ -962,9 +962,11 @@ struct StatPass : public Pass {
continue;
}
if (args[argidx] == "-top" && argidx + 1 < args.size()) {
if (design->module(RTLIL::escape_id(args[argidx + 1])) == nullptr)
TwineRef top_ref = TwineSearch(&design->twines).find(RTLIL::escape_id(args[argidx + 1]));
if (design->module(top_ref) == nullptr)
log_cmd_error("Can't find module %s.\n", args[argidx + 1]);
top_mod = design->module(RTLIL::escape_id(args[++argidx]));
top_mod = design->module(top_ref);
argidx++;
continue;
}
if (args[argidx] == "-json") {