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twine: avoid TwinePool::lookup

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 22:57:13 +02:00
parent 4061593ce5
commit 3a5f5c77bf
23 changed files with 277 additions and 259 deletions
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29
passes/cmds/design.cc
View file

@ -254,21 +254,22 @@ struct DesignPass : public Pass {
if (import_mode)
{
std::string prefix = RTLIL::escape_id(as_name);
TwineRef as_name_ref = copy_to_design->twines.add(std::string{prefix});
pool<Module*> queue;
dict<IdString, IdString> done;
if (copy_to_design->module(prefix) != nullptr)
copy_to_design->remove(copy_to_design->module(prefix));
if (copy_to_design->module(as_name_ref) != nullptr)
copy_to_design->remove(copy_to_design->module(as_name_ref));
if (GetSize(copy_src_modules) != 1)
log_cmd_error("No top module found in source design.\n");
for (auto mod : copy_src_modules)
{
log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix));
log("Importing %s as %s.\n", mod, design->twines.unescaped_str(as_name_ref));
RTLIL::Module *t = mod->clone(copy_to_design, copy_to_design->twines.add(Twine{prefix}));
RTLIL::Module *t = mod->clone(copy_to_design, as_name_ref);
t->attributes.erase(ID::top);
queue.insert(t);
@ -290,21 +291,22 @@ struct DesignPass : public Pass {
if (done.count(cell->type) == 0)
{
std::string trg_name = prefix + "." + (cell->type.unescape());
std::string trg_name = prefix + "." + cell->type.unescape();
TwineRef trg_ref = copy_to_design->twines.add(std::string{trg_name});
log("Importing %s as %s.\n", fmod, RTLIL::unescape_id(trg_name));
log("Importing %s as %s.\n", log_id(fmod), RTLIL::unescape_id(trg_name).c_str());
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
if (copy_to_design->module(trg_ref) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_ref));
RTLIL::Module *t = fmod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
RTLIL::Module *t = fmod->clone(copy_to_design, trg_ref);
t->attributes.erase(ID::top);
queue.insert(t);
done[cell->type] = trg_name;
}
cell->type_impl = cell->module->design->twines.add(Twine{done.at(cell->type).str()});
cell->type_impl = cell->module->design->twines.add(std::string{done.at(cell->type).str()});
}
}
}
@ -317,11 +319,12 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules)
{
std::string trg_name = as_name.empty() ? copy_from_design->twines.str(mod->meta_->name) : RTLIL::escape_id(as_name);
TwineRef trg_ref = copy_to_design->twines.add(std::string{trg_name});
if (copy_to_design->module(trg_name) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_name));
if (copy_to_design->module(trg_ref) != nullptr)
copy_to_design->remove(copy_to_design->module(trg_ref));
mod->clone(copy_to_design, copy_to_design->twines.add(Twine{trg_name}));
mod->clone(copy_to_design, trg_ref);
}
}

32
passes/cmds/select.cc
View file

@ -273,7 +273,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{
if (design->module(cell->type_impl) == nullptr)
continue;
lhs.selected_modules.insert(design->twines.add(Twine{cell->type.str()}));
lhs.selected_modules.insert(design->twines.add(std::string{cell->type.str()}));
}
}
}
@ -286,7 +286,7 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &
if (lhs.selected_module(mod->meta_->name))
for (auto cell : mod->cells())
if (lhs.selected_member(mod->meta_->name, cell->meta_->name) && (design->module(cell->type_impl) != nullptr))
new_sel.selected_modules.insert(design->twines.add(Twine{cell->type.str()}));
new_sel.selected_modules.insert(design->twines.add(std::string{cell->type.str()}));
lhs = new_sel;
}
@ -295,7 +295,7 @@ static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &l
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
for (auto mod : design->modules())
for (auto cell : mod->cells())
if ((design->module(cell->type_impl) != nullptr) && lhs.selected_whole_module(design->twines.add(Twine{cell->type.str()})))
if ((design->module(cell->type_impl) != nullptr) && lhs.selected_whole_module(design->twines.add(std::string{cell->type.str()})))
new_sel.selected_members[mod->meta_->name].insert(cell->meta_->name);
lhs = new_sel;
}
@ -1480,7 +1480,7 @@ struct SelectPass : public Pass {
}
IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
IdString obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
sel.selected_members[design->twines.add(Twine{mod_name.str()})].insert(design->twines.add(Twine{obj_name.str()}));
sel.selected_members[design->twines.add(std::string{mod_name.str()})].insert(design->twines.add(std::string{obj_name.str()}));
}
select_filter_active_mod(design, sel);
@ -1745,6 +1745,7 @@ struct CdPass : public Pass {
design->push_full_selection();
design->selected_active_module = TwineRef{};
TwineSearch search(&design->twines);
while (1)
{
size_t pos = modname.rfind('.');
@ -1753,12 +1754,13 @@ struct CdPass : public Pass {
break;
modname = modname.substr(0, pos);
Module *mod = design->module(RTLIL::IdString(modname));
TwineRef mod_ref = search.find(modname);
Module *mod = design->module(mod_ref);
if (mod == nullptr)
continue;
design->selected_active_module = design->twines.add(Twine{modname});
design->selected_active_module = mod_ref;
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
@ -1769,17 +1771,18 @@ struct CdPass : public Pass {
return;
}
std::string modname = RTLIL::escape_id(args[1]);
TwineSearch search(&design->twines);
TwineRef modname = search.find(RTLIL::escape_id(args[1]));
if (design->module(RTLIL::IdString(modname)) == nullptr && design->selected_active_module) {
if (design->module(modname) == nullptr && design->selected_active_module) {
RTLIL::Module *module = design->module(design->selected_active_module);
TwineRef cell_ref = design->twines.lookup(modname);
TwineRef cell_ref = modname;
if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
modname = design->twines.str(module->cell(cell_ref)->type.ref());
modname = module->cell(cell_ref)->type_impl;
}
if (design->module(RTLIL::IdString(modname)) != nullptr) {
design->selected_active_module = design->twines.add(Twine{modname});
if (design->module(modname) != nullptr) {
design->selected_active_module = modname;
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
@ -1787,7 +1790,7 @@ struct CdPass : public Pass {
return;
}
log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname));
log_cmd_error("No such module `%s' found!\n", design->twines.str(modname));
}
} CdPass;
@ -1844,8 +1847,9 @@ struct LsPass : public Pass {
if (!matches.empty()) {
log("\n%d %s:\n", int(matches.size()), "modules");
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
TwineSearch search(&design->twines);
for (auto id : matches)
log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(id)) ? "" : "*");
log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(search.find(id.str()))) ? "" : "*");
}
}
else

7
passes/cmds/show.cc
View file

@ -56,6 +56,7 @@ struct ShowWorker
FILE *f;
RTLIL::Design *design;
TwineSearch search;
RTLIL::Module *module;
uint32_t currentColor;
bool genWidthLabels;
@ -148,7 +149,7 @@ struct ShowWorker
std::string findColor(IdString member_name)
{
TwineRef member_ref = design->twines.lookup(member_name.str());
TwineRef member_ref = search.find(member_name.str());
for (auto &s : color_selections)
if (member_ref && s.second.selected_member(module->meta_->name, member_ref)) {
return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
@ -175,7 +176,7 @@ struct ShowWorker
const char *findLabel(std::string member_name)
{
TwineRef member_ref = design->twines.lookup(member_name);
TwineRef member_ref = search.find(member_name);
for (auto &s : label_selections)
if (member_ref && s.second.selected_member(module->meta_->name, member_ref))
return escape(s.first);
@ -627,7 +628,7 @@ struct ShowWorker
const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::IdString colorattr) :
f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
f(f), design(design), search(&design->twines), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
{

10
passes/cmds/stat.cc
View file

@ -261,7 +261,7 @@ struct statdata_t {
} else if (it == "S") {
port_name = TW::S;
} else {
port_name = design->twines.add(Twine{it});
port_name = design->twines.add(std::string{it});
}
if (cell->hasPort(port_name)) {
int width = GetSize(cell->getPort(port_name));
@ -886,7 +886,7 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
if (ar != nullptr && !ar->value.empty()) {
string prefix = cell->args[0].substr(0, 1) == "$" ? "" : "\\";
// TwineRef t = twines.add(Twine{prefix + cell->args[0]});
// TwineRef t = twines.add(std::string{prefix + cell->args[0]});
IdString t = prefix + cell->args[0];
cell_area[t] = {atof(ar->value.c_str()), is_flip_flop, single_parameter_area, double_parameter_area,
port_names};
@ -962,9 +962,11 @@ struct StatPass : public Pass {
continue;
}
if (args[argidx] == "-top" && argidx + 1 < args.size()) {
if (design->module(RTLIL::escape_id(args[argidx + 1])) == nullptr)
TwineRef top_ref = TwineSearch(&design->twines).find(RTLIL::escape_id(args[argidx + 1]));
if (design->module(top_ref) == nullptr)
log_cmd_error("Can't find module %s.\n", args[argidx + 1]);
top_mod = design->module(RTLIL::escape_id(args[++argidx]));
top_mod = design->module(top_ref);
argidx++;
continue;
}
if (args[argidx] == "-json") {

64
passes/hierarchy/hierarchy.cc
View file

@ -119,11 +119,11 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
log_assert(indices.empty());
RTLIL::Module *mod = design->addModule(design->twines.add(Twine{celltype.str()}));
RTLIL::Module *mod = design->addModule(design->twines.add(std::string{celltype.str()}));
mod->attributes[ID::blackbox] = RTLIL::Const(1);
for (auto &decl : ports) {
RTLIL::Wire *wire = mod->addWire(design->twines.add(Twine{decl.portname}), portwidths.at(decl.portname));
RTLIL::Wire *wire = mod->addWire(design->twines.add(std::string{decl.portname}), portwidths.at(decl.portname));
wire->port_id = decl.index;
wire->port_input = decl.input;
wire->port_output = decl.output;
@ -284,8 +284,8 @@ struct IFExpander
for (auto mod_wire : mod_replace_ports->wires()) {
std::string signal_name1 = conn_name_str + "." + design.twines.unescaped_str(mod_wire->name.ref());
std::string signal_name2 = interface_name.str() + "." + design.twines.unescaped_str(mod_wire->name.ref());
connections_to_add.push_back(design.twines.add(Twine{signal_name1}));
TwineRef signal_name2_ref = design.twines.lookup(signal_name2);
connections_to_add.push_back(design.twines.add(std::string{signal_name1}));
TwineRef signal_name2_ref = TwineSearch(&design.twines).find(signal_name2);
if(module.wire(signal_name2_ref) == nullptr) {
log_error("Could not find signal '%s' in '%s'\n",
signal_name2.c_str(), design.twines.str(module.meta_->name).data());
@ -389,11 +389,11 @@ RTLIL::Module *get_module(RTLIL::Design &design,
const std::vector<std::string> &libdirs)
{
std::string cell_type = design.twines.str(cell.type.ref());
RTLIL::Module *abs_mod = design.module("$abstract" + cell_type);
RTLIL::Module *abs_mod = design.module(TwineSearch(&design.twines).find("$abstract" + cell_type));
if (abs_mod) {
cell.type_impl = design.twines.add(Twine{design.twines.str(abs_mod->derive(&design, cell.parameters))});
cell.type_impl = design.twines.add(std::string{design.twines.str(abs_mod->derive(&design, cell.parameters))});
cell.parameters.clear();
RTLIL::Module *mod = design.module(cell.type);
RTLIL::Module *mod = design.module(cell.type.ref());
log_assert(mod);
return mod;
}
@ -417,7 +417,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
continue;
Frontend::frontend_call(&design, NULL, filename, ext.second);
RTLIL::Module *mod = design.module(cell.type);
RTLIL::Module *mod = design.module(cell.type.ref());
if (!mod)
log_error("File `%s' from libdir does not declare module `%s'.\n",
filename.c_str(), cell_type.c_str());
@ -514,7 +514,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str());
int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str());
array_cells[cell] = std::pair<int, int>(idx, num);
cell->type_impl = cell->module->design->twines.add(Twine{cell->type.str().substr(pos_type + 1)});
cell->type_impl = cell->module->design->twines.add(std::string{cell->type.str().substr(pos_type + 1)});
}
dict<TwineRef, RTLIL::Module*> interfaces_by_name;
@ -575,7 +575,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &p : if_expander.interfaces_to_add_to_submodule)
interfaces_by_name[p.first] = p.second;
for (auto &p : if_expander.modports_used_in_submodule)
modports_by_name[p.first] = design->twines.add(Twine{p.second.str()});
modports_by_name[p.first] = design->twines.add(std::string{p.second.str()});
cell->type_impl = mod->derive(design,
cell->parameters,
interfaces_by_name,
@ -663,12 +663,13 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTL
log("Used module: %*s%s\n", indent, "", mod->design->twines.str(mod->meta_->name).data());
used.insert(mod);
TwineSearch search(&design->twines);
for (auto cell : mod->cells()) {
std::string celltype = cell->type.str();
if (celltype.compare(0, strlen("$array:"), "$array:") == 0)
celltype = basic_cell_type(celltype);
if (design->module(celltype))
hierarchy_worker(design, used, design->module(celltype), indent+4);
if (RTLIL::Module *cm = design->module(search.find(celltype)))
hierarchy_worker(design, used, cm, indent+4);
}
}
@ -712,9 +713,9 @@ bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{
if (cache.count(mod) == 0)
for (auto c : mod->cells()) {
if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()}))
if (mod->meta_->name == mod->design->twines.add(std::string{c->type.str()}))
continue;
RTLIL::Module *m = mod->design->module(c->type);
RTLIL::Module *m = mod->design->module(c->type.ref());
if ((m != nullptr && set_keep_print(cache, m)) || c->type == TW($print))
return cache[mod] = true;
}
@ -725,9 +726,9 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
{
if (cache.count(mod) == 0)
for (auto c : mod->cells()) {
if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()}))
if (mod->meta_->name == mod->design->twines.add(std::string{c->type.str()}))
continue;
RTLIL::Module *m = mod->design->module(c->type);
RTLIL::Module *m = mod->design->module(c->type.ref());
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(TW($check), TW($assert), TW($assume), TW($live), TW($fair), TW($cover)))
return cache[mod] = true;
}
@ -745,7 +746,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
if (celltype.compare(0, strlen("$array:"), "$array:") == 0)
celltype = basic_cell_type(celltype);
// Is this cell a module instance?
auto instModule = design->module(celltype);
auto instModule = design->module(TwineSearch(&design->twines).find(celltype));
// If there is no instance for this, issue a warning.
if (instModule != nullptr) {
score = max(score, find_top_mod_score(design, instModule, db) + 1);
@ -775,16 +776,17 @@ RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::stri
{
const std::string &cellname = cell->name.str();
size_t idx = cellname.size();
TwineSearch search(&module->design->twines);
while ((idx = cellname.find_last_of('.', idx-1)) != std::string::npos) {
std::string wire_name = cellname.substr(0, idx+1) + port.substr(1);
TwineRef ref = module->design->twines.lookup(wire_name);
TwineRef ref = search.find(wire_name);
if (ref != Twine::Null) {
Wire *found = module->wire(ref);
if (found != nullptr)
return found;
}
}
TwineRef ref = module->design->twines.lookup(port);
TwineRef ref = search.find(port);
if (ref != Twine::Null)
return module->wire(ref);
return nullptr;
@ -1014,10 +1016,12 @@ struct HierarchyPass : public Pass {
{
IdString top_name = RTLIL::escape_id(load_top_mod);
IdString abstract_id = "$abstract" + RTLIL::escape_id(load_top_mod);
top_mod = design->module(top_name);
TwineSearch search(&design->twines);
top_mod = design->module(search.find(top_name.str()));
RTLIL::Module *abstract_mod = design->module(search.find(abstract_id.str()));
dict<RTLIL::IdString, RTLIL::Const> top_parameters;
if ((top_mod == nullptr && design->module(abstract_id)) || top_mod != nullptr) {
if ((top_mod == nullptr && abstract_mod) || top_mod != nullptr) {
for (auto &para : parameters) {
SigSpec sig_value;
if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
@ -1026,12 +1030,12 @@ struct HierarchyPass : public Pass {
}
}
if (top_mod == nullptr && design->module(abstract_id))
top_mod = design->module(design->module(abstract_id)->derive(design, top_parameters));
if (top_mod == nullptr && abstract_mod)
top_mod = design->module(abstract_mod->derive(design, top_parameters));
else if (top_mod != nullptr && !top_parameters.empty())
top_mod = design->module(top_mod->derive(design, top_parameters));
TwineRef top_name_ref = design->twines.add(Twine{top_name.str()});
TwineRef top_name_ref = design->twines.add(std::string{top_name.str()});
if (top_mod != nullptr && top_mod->meta_->name != top_name_ref) {
Module *m = top_mod->clone();
m->meta_->name = top_name_ref;
@ -1119,7 +1123,7 @@ struct HierarchyPass : public Pass {
top_mod = design->module(top_mod->derive(design, top_parameters));
TwineRef top_name_ref = design->twines.add(Twine{top_name.str()});
TwineRef top_name_ref = design->twines.add(std::string{top_name.str()});
if (top_mod != nullptr && top_mod->meta_->name != top_name_ref) {
Module *m = top_mod->clone();
m->meta_->name = top_name_ref;
@ -1296,7 +1300,7 @@ struct HierarchyPass : public Pass {
id, module, cell, cell->type.unescaped());
new_connections_twine[conn.first] = conn.second;
} else
new_connections_twine[design->twines.add(Twine{pos_map.at(key).str()})] = conn.second;
new_connections_twine[design->twines.add(std::string{pos_map.at(key).str()})] = conn.second;
} else
new_connections_twine[conn.first] = conn.second;
}
@ -1335,8 +1339,7 @@ struct HierarchyPass : public Pass {
if (new_m_ref == TwineRef{})
continue;
if (new_m_ref != m->meta_->name) {
IdString new_m_name(std::string(design->twines.str(new_m_ref)));
m = design->module(new_m_name);
m = design->module(new_m_ref);
blackbox_derivatives.insert(m);
}
}
@ -1388,7 +1391,7 @@ struct HierarchyPass : public Pass {
}
for (auto &it : defaults_db.at(cell->type)) {
TwineRef port_ref = design->twines.add(Twine{it.first.str()});
TwineRef port_ref = design->twines.add(std::string{it.first.str()});
if (!cell->hasPort(port_ref))
cell->setPort(port_ref, it.second);
}
@ -1525,8 +1528,7 @@ struct HierarchyPass : public Pass {
if (new_m_ref == TwineRef{})
continue;
if (new_m_ref != m->meta_->name) {
IdString new_m_name(std::string(design->twines.str(new_m_ref)));
m = design->module(new_m_name);
m = design->module(new_m_ref);
blackbox_derivatives.insert(m);
}
} else {

2
passes/opt/opt_clean/cells_all.cc
View file

@ -326,7 +326,7 @@ void remove_mems(RTLIL::Module* mod, const MemAnalysis& mem_analysis, bool verbo
if (!mem_analysis.unused[it.second].load(std::memory_order_relaxed))
continue;
std::string id_s = it.first;
TwineRef id = mod->design->twines.add(Twine{it.first});
TwineRef id = mod->design->twines.add(std::string{it.first});
if (verbose)
log_debug(" removing unused memory `%s'.\n", id_s);
delete mod->memories.at(id);

11
passes/opt/opt_clean/wires.cc
View file

@ -144,12 +144,11 @@ bool compare_signals(const RTLIL::SigBit &s1, const RTLIL::SigBit &s2, const Sha
return w2->name.lt_by_name(w1->name);
}
bool check_public_name(RTLIL::IdString id)
bool check_public_name(const std::string &id_str)
{
if (id.begins_with("$"))
if (!id_str.empty() && id_str[0] == '$')
return false;
const std::string &id_str = id.str();
if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
if (id_str.rfind("\\_", 0) == 0 && (id_str.back() == '_' || id_str.find("_[") != std::string::npos))
return false;
if (id_str.find(".$") != std::string::npos)
return false;
@ -438,7 +437,7 @@ struct WireDeleter {
if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
// do not delete anything with "keep" or module ports or initialized wires
} else
if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
if (!purge_mode && check_public_name(wire->name.escaped()) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
} else
if (!check_any(used_sig_analysis.raw_connected, s1)) {
@ -520,7 +519,7 @@ struct WireDeleter {
int delete_wires(RTLIL::Module* mod, bool verbose) {
int deleted_and_unreported = 0;
for (auto wire : del_wires_queue) {
if (ys_debug() || (check_public_name(wire->name) && verbose))
if (ys_debug() || (check_public_name(wire->name.escaped()) && verbose))
log_debug(" removing unused non-port wire %s.\n", wire->name);
else
deleted_and_unreported++;

2
passes/opt/opt_expr.cc
View file

@ -421,7 +421,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, TwineRe
twines.unescaped_str(port), cell->type.unescaped(), cell, cell->module,
log_signal(sig), log_signal(new_sig));
cell->setPort(port, new_sig);
cell->type_impl = cell->module->design->twines.add(Twine{cell->type == type1 ? type2 : type1});
cell->type_impl = cell->module->design->twines.add(std::string{cell->type == type1 ? type2 : type1});
}
}
}

2
passes/opt/rmports.cc
View file

@ -77,7 +77,7 @@ struct RmportsPassPass : public Pass {
{
log(" Removing port \"%s\" from instance \"%s\"\n",
p.c_str(), cell->type);
cell->unsetPort(cell->module->design->twines.add(Twine{p.str()}));
cell->unsetPort(cell->module->design->twines.add(std::string{p.str()}));
}
}
}

8
passes/opt/wreduce.cc
View file

@ -244,7 +244,7 @@ struct WreduceWorker
{
port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
auto &twines = cell->module->design->twines;
SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
SigSpec sig = mi.sigmap(cell->getPort(twines.add(std::string{stringf("\\%c", port)})));
if (port == 'B' && cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr)))
port_signed = false;
@ -268,8 +268,8 @@ struct WreduceWorker
if (bits_removed) {
log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescaped());
// SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", port)})));
cell->setPort(twines.add(Twine{stringf("\\%c", port)}), sig);
// SigSpec sig = mi.sigmap(cell->getPort(twines.add(std::string{stringf("\\%c", port)})));
cell->setPort(twines.add(std::string{stringf("\\%c", port)}), sig);
did_something = true;
}
}
@ -640,7 +640,7 @@ struct WreducePass : public Pass {
if (!opt_memx && c->type.in(TW($memrd), TW($memrd_v2), TW($memwr), TW($memwr_v2), TW($meminit), TW($meminit_v2))) {
std::string memid_s = c->getParam(ID::MEMID).decode_string();
TwineRef memid = design->twines.add(Twine{memid_s});
TwineRef memid = design->twines.add(std::string{memid_s});
RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) {
int cur_addrbits = c->getParam(ID::ABITS).as_int();

7
passes/proc/proc_arst.cc
View file

@ -288,11 +288,14 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design);
pool<Wire*> delete_initattr_wires;
TwineRef global_arst_ref = global_arst.empty() ? Twine::Null
: TwineSearch(&design->twines).find(global_arst);
for (auto mod : design->all_selected_modules()) {
SigMap assign_map(mod);
for (auto proc : mod->selected_processes()) {
proc_arst(mod, proc, assign_map);
if (global_arst.empty() || mod->wire(design->twines.lookup(global_arst)) == nullptr)
if (global_arst_ref == Twine::Null || mod->wire(global_arst_ref) == nullptr)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc->syncs)
@ -316,7 +319,7 @@ struct ProcArstPass : public Pass {
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
sync->signal = mod->wire(design->twines.lookup(global_arst));
sync->signal = mod->wire(global_arst_ref);
sync->actions = arst_actions;
proc->syncs.push_back(sync);
}

4
passes/proc/proc_dff.cc
View file

@ -94,7 +94,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, TW($aldff));
RTLIL::Cell *cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), TW($aldff));
cell->attributes = proc->attributes;
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
@ -116,7 +116,7 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff));
RTLIL::Cell *cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff));
cell->attributes = proc->attributes;
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());

12
passes/proc/proc_mux.cc
View file

@ -155,7 +155,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
std::stringstream sstr;
sstr << "$procmux$" << (autoidx++);
RTLIL::Wire *cmp_wire = mod->addWire(Twine{sstr.str() + "_CMP"}, 0);
RTLIL::Wire *cmp_wire = mod->addWire(mod->design->twines.add(std::string{sstr.str() + "_CMP"}), 0);
for (auto comp : compare)
{
@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
else
{
// create compare cell
RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? TW($eqx) : TW($eq));
RTLIL::Cell *eq_cell = mod->addCell(mod->design->twines.add(std::string{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}), ifxmode ? TW($eqx) : TW($eq));
apply_attrs(eq_cell, sw, cs);
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
@ -201,10 +201,10 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
}
else
{
ctrl_wire = mod->addWire(Twine{sstr.str() + "_CTRL"});
ctrl_wire = mod->addWire(mod->design->twines.add(std::string{sstr.str() + "_CTRL"}));
// reduce cmp vector to one logic signal
RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, TW($reduce_or));
RTLIL::Cell *any_cell = mod->addCell(mod->design->twines.add(std::string{sstr.str() + "_ANY"}), TW($reduce_or));
apply_attrs(any_cell, sw, cs);
any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
@ -236,10 +236,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
log_assert(ctrl_sig.size() == 1);
// prepare multiplexer output signal
RTLIL::Wire *result_wire = mod->addWire(Twine{sstr.str() + "_Y"}, when_signal.size());
RTLIL::Wire *result_wire = mod->addWire(mod->design->twines.add(std::string{sstr.str() + "_Y"}), when_signal.size());
// create the multiplexer itself
RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, TW($mux));
RTLIL::Cell *mux_cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), TW($mux));
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());